targets/ulx3s: get memtest working by disabling sdram refresh

[litex.git] / litex / boards / platforms / versaecp55g.py

diff --git a/litex/boards/platforms/versaecp55g.py b/litex/boards/platforms/versaecp55g.py
index 7b0fb4649ff2d3bf003c82996f3164a65c450c04..8ecb263333f6ea4f220272914c5bbaf721e18c6f 100644 (file)
--- a/litex/boards/platforms/versaecp55g.py
+++ b/litex/boards/platforms/versaecp55g.py
@@ -29,10 +29,11 @@ _io = [
     ("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
 
     ("serial", 0,
-        Subsignal("tx", Pins("A12"), IOStandard("LVCMOS33")),  # X4 IO0
-        Subsignal("rx", Pins("A13"), IOStandard("LVCMOS33")),  # X4 IO1
+        Subsignal("rx", Pins("C11"), IOStandard("LVCMOS33")),
+        Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
     ),
 
+
     ("eth_clocks", 0,
         Subsignal("tx", Pins("P19")),
         Subsignal("rx", Pins("L20")),