from litex.boards.platforms import netv2
from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
-from litedram.modules import MT41J128M16
+from litedram.modules import K4B2G1646F
from litedram.phy import s7ddrphy
from liteeth.phy.rmii import LiteEthPHYRMII
-from liteeth.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+ self.clock_domains.cd_sys = ClockDomain()
+ self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
- self.clock_domains.cd_clk200 = ClockDomain()
- self.clock_domains.cd_clk100 = ClockDomain()
- self.clock_domains.cd_eth = ClockDomain()
+ self.clock_domains.cd_clk200 = ClockDomain()
+ self.clock_domains.cd_clk100 = ClockDomain()
+ self.clock_domains.cd_eth = ClockDomain()
# # #
- self.cd_sys.clk.attr.add("keep")
- self.cd_sys4x.clk.attr.add("keep")
- self.cd_sys4x_dqs.clk.attr.add("keep")
-
self.submodules.pll = pll = S7PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk50"), 50e6)
- pll.create_clkout(self.cd_sys, sys_clk_freq)
- pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
+ pll.create_clkout(self.cd_sys, sys_clk_freq)
+ pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
- pll.create_clkout(self.cd_clk200, 200e6)
- pll.create_clkout(self.cd_clk100, 100e6)
- pll.create_clkout(self.cd_eth, 50e6)
+ pll.create_clkout(self.cd_clk200, 200e6)
+ pll.create_clkout(self.cd_clk100, 100e6)
+ pll.create_clkout(self.cd_eth, 50e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# BaseSoC ------------------------------------------------------------------------------------------
-class BaseSoC(SoCSDRAM):
- def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
+class BaseSoC(SoCCore):
+ def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
platform = netv2.Platform()
- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
- integrated_rom_size=integrated_rom_size,
- integrated_sram_size=0x8000,
- **kwargs)
- self.submodules.crg = _CRG(platform, sys_clk_freq)
+ # SoCCore ---------------------------------------------------------------------------------
+ SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
- # sdram
- self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
- self.add_csr("ddrphy")
- sdram_module = MT41J128M16(sys_clk_freq, "1:4")
- self.register_sdram(self.ddrphy,
- sdram_module.geom_settings,
- sdram_module.timing_settings)
-
-# EthernetSoC --------------------------------------------------------------------------------------
-
-class EthernetSoC(BaseSoC):
- mem_map = {
- "ethmac": 0xb0000000,
- }
- mem_map.update(BaseSoC.mem_map)
-
- def __init__(self, **kwargs):
- BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
-
- self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
- self.platform.request("eth"))
- self.add_csr("ethphy")
- self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
- interface="wishbone", endianness=self.cpu.endianness)
- self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
- self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
- self.add_csr("ethmac")
- self.add_interrupt("ethmac")
-
- self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
- self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
- self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
- self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
- self.platform.add_false_path_constraints(
- self.crg.cd_sys.clk,
- self.ethphy.crg.cd_eth_rx.clk,
- self.ethphy.crg.cd_eth_tx.clk)
+ # CRG --------------------------------------------------------------------------------------
+ self.submodules.crg = _CRG(platform, sys_clk_freq)
+ # DDR3 SDRAM -------------------------------------------------------------------------------
+ if not self.integrated_main_ram_size:
+ self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
+ memtype = "DDR3",
+ nphases = 4,
+ sys_clk_freq = sys_clk_freq)
+ self.add_csr("ddrphy")
+ self.add_sdram("sdram",
+ phy = self.ddrphy,
+ module = K4B2G1646F(sys_clk_freq, "1:4"),
+ origin = self.mem_map["main_ram"],
+ size = kwargs.get("max_sdram_size", 0x40000000),
+ l2_cache_size = kwargs.get("l2_size", 8192),
+ l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
+ l2_cache_reverse = True
+ )
+
+ # Ethernet ---------------------------------------------------------------------------------
+ if with_ethernet:
+ self.submodules.ethphy = LiteEthPHYRMII(
+ clock_pads = self.platform.request("eth_clocks"),
+ pads = self.platform.request("eth"))
+ self.add_csr("ethphy")
+ self.add_ethernet(phy=self.ethphy)
# Build --------------------------------------------------------------------------------------------
help="enable Ethernet support")
args = parser.parse_args()
- cls = EthernetSoC if args.with_ethernet else BaseSoC
- soc = cls(**soc_sdram_argdict(args))
+ soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
projects / litex.git / blobdiff