targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed to trellis

[litex.git] / litex / boards / targets / versa_ecp5.py

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 1e3e6c70d337efd065e2158537b9d271a8ea4840..eb1bfeffdfaf46339a51053a42cf33db2bd3a052 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -58,7 +58,7 @@ class _CRG(Module):
 
 class BaseSoC(SoCSDRAM):
     def __init__(self, **kwargs):
-        platform = versa_ecp5.Platform(toolchain="prjtrellis")
+        platform = versa_ecp5.Platform(toolchain="trellis")
         platform.add_extension(versa_ecp5._ecp5_soc_hat_io)
         sys_clk_freq = int(50e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,