litex_sim: Rework Makefiles to put output files in gateware directory.

[litex.git] / litex / build / sim / verilator.py

diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 5270e3301741655059e7003bbb0ad5083a620eb1..f068d08d1f899c08b0d03d4983973cfba2c1343c 100644 (file)
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -125,7 +125,6 @@ def _build_sim(build_name, sources, threads, coverage, opt_level="O3", trace_fst
     build_script_contents = """\
 rm -rf obj_dir/
 make -C . -f {} {} {} {} {} {}
-mkdir -p modules && cp obj_dir/*.so modules
 """.format(makefile,
     "CC_SRCS=\"{}\"".format("".join(cc_srcs)),
     "THREADS={}".format(threads) if int(threads) > 1 else "",
@@ -170,7 +169,7 @@ def _run_sim(build_name, as_root=False):
 
 class SimVerilatorToolchain:
     def build(self, platform, fragment, build_dir="build", build_name="dut",
-            toolchain_path=None, serial="console", build=True, run=True, threads=1,
+            serial="console", build=True, run=True, threads=1,
             verbose=True, sim_config=None, coverage=False, opt_level="O0",
             trace=False, trace_fst=False, trace_start=0, trace_end=-1):
 
@@ -217,4 +216,4 @@ class SimVerilatorToolchain:
         os.chdir("../../")
 
         if build:
-            return top_output.ns
\ No newline at end of file
+            return top_output.ns