gen/fhdl/verilog: list available clock domains on keyerror

[litex.git] / litex / gen / fhdl / verilog.py

diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 1fb6024b37d0fbc0372816dce7f270a9646f159f..d5aef8d6d4f6ad0fbddf7cd20d9b95484ad272bc 100644 (file)
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -339,6 +339,9 @@ def convert(f, ios=None, name="top",
                 f.clock_domains.append(cd)
                 ios |= {cd.clk, cd.rst}
             else:
+                print("available clock domains:")
+                for f in f.clock_domains:
+                    print(f.name)
                 raise KeyError("Unresolved clock domain: '"+cd_name+"'")
 
     f = lower_complex_slices(f)