+# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
+# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2019 Mateusz Holenko <mholenko@antmicro.com>
+# This file is Copyright (c) 2018 Peter Gielda <pgielda@antmicro.com>
+# This file is Copyright (c) 2018 Sergiusz Bazanski <q3k@q3k.org>
+# This file is Copyright (c) 2016-2017 Tim 'mithro' Ansell <mithro@mithis.com>
+# This file is Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
+# License: BSD
+
+
import os
import subprocess
import struct
import shutil
from litex.build.tools import write_to_file
-from litex.soc.integration import cpu_interface, soc_sdram, sdram_init
+from litex.soc.integration import cpu_interface, soc_core, soc_sdram
+from litedram import sdram_init
__all__ = ["soc_software_packages", "soc_directory",
"Builder", "builder_args", "builder_argdict"]
def __init__(self, soc, output_dir=None,
compile_software=True, compile_gateware=True,
gateware_toolchain_path=None,
- csr_csv=None):
+ csr_json=None, csr_csv=None):
self.soc = soc
if output_dir is None:
output_dir = "soc_{}_{}".format(
self.compile_gateware = compile_gateware
self.gateware_toolchain_path = gateware_toolchain_path
self.csr_csv = csr_csv
+ self.csr_json = csr_json
self.software_packages = []
for name in soc_software_packages:
cpu_type = self.soc.cpu_type
memory_regions = self.soc.get_memory_regions()
flash_boot_address = getattr(self.soc, "flash_boot_address", None)
+ shadow_base = getattr(self.soc, "shadow_base", None)
csr_regions = self.soc.get_csr_regions()
constants = self.soc.get_constants()
- if isinstance(self.soc, soc_sdram.SoCSDRAM) and self.soc._sdram_phy:
- sdram_phy_settings = self.soc._sdram_phy[0].settings
- else:
- sdram_phy_settings = None
buildinc_dir = os.path.join(self.output_dir, "software", "include")
generated_dir = os.path.join(buildinc_dir, "generated")
variables_contents = []
def define(k, v):
variables_contents.append("{}={}\n".format(k, _makefile_escape(v)))
- for k, v in cpu_interface.get_cpu_mak(cpu_type):
+ for k, v in cpu_interface.get_cpu_mak(self.soc.cpu):
+ define(k, v)
+ # Distinguish between LiteX and MiSoC.
+ define("LITEX", "1")
+ # Distinguish between applications running from main RAM and
+ # flash for user-provided software packages.
+ exec_profiles = {
+ "COPY_TO_MAIN_RAM" : "0",
+ "EXECUTE_IN_PLACE" : "0"
+ }
+ if "main_ram" in (m[0] for m in memory_regions):
+ exec_profiles["COPY_TO_MAIN_RAM"] = "1"
+ else:
+ exec_profiles["EXECUTE_IN_PLACE"] = "1"
+ for k, v in exec_profiles.items():
define(k, v)
define("SOC_DIRECTORY", soc_directory)
variables_contents.append("export BUILDINC_DIRECTORY\n")
write_to_file(
os.path.join(generated_dir, "variables.mak"),
"".join(variables_contents))
-
write_to_file(
os.path.join(generated_dir, "output_format.ld"),
- cpu_interface.get_linker_output_format(cpu_type))
+ cpu_interface.get_linker_output_format(self.soc.cpu))
write_to_file(
os.path.join(generated_dir, "regions.ld"),
cpu_interface.get_linker_regions(memory_regions))
-
write_to_file(
os.path.join(generated_dir, "mem.h"),
- cpu_interface.get_mem_header(memory_regions, flash_boot_address))
+ cpu_interface.get_mem_header(memory_regions, flash_boot_address, shadow_base))
write_to_file(
os.path.join(generated_dir, "csr.h"),
cpu_interface.get_csr_header(csr_regions, constants))
-
- if sdram_phy_settings is not None:
- write_to_file(
- os.path.join(generated_dir, "sdram_phy.h"),
- sdram_init.get_sdram_phy_header(sdram_phy_settings))
-
- def _generate_csr_csv(self):
+ write_to_file(
+ os.path.join(generated_dir, "git.h"),
+ cpu_interface.get_git_header()
+ )
+
+ if isinstance(self.soc, soc_sdram.SoCSDRAM):
+ if hasattr(self.soc, "sdram"):
+ write_to_file(
+ os.path.join(generated_dir, "sdram_phy.h"),
+ sdram_init.get_sdram_phy_c_header(
+ self.soc.sdram.controller.settings.phy,
+ self.soc.sdram.controller.settings.timing))
+
+ def _generate_csr_map(self, csr_json=None, csr_csv=None):
memory_regions = self.soc.get_memory_regions()
csr_regions = self.soc.get_csr_regions()
constants = self.soc.get_constants()
- csr_dir = os.path.dirname(self.csr_csv)
- os.makedirs(csr_dir, exist_ok=True)
- write_to_file(
- self.csr_csv,
- cpu_interface.get_csr_csv(csr_regions, constants, memory_regions))
+ shadow_base = getattr(self.soc, "shadow_base", None)
+ if shadow_base:
+ constants.append(('shadow_base', shadow_base))
+
+ flash_boot_address = getattr(self.soc, "flash_boot_address", None)
+ if flash_boot_address:
+ constants.append(('flash_boot_address', flash_boot_address))
+
+ if csr_json is not None:
+ csr_dir = os.path.dirname(os.path.realpath(csr_json))
+ os.makedirs(csr_dir, exist_ok=True)
+ write_to_file(csr_json, cpu_interface.get_csr_json(csr_regions, constants, memory_regions))
+
+ if csr_csv is not None:
+ csr_dir = os.path.dirname(os.path.realpath(csr_csv))
+ os.makedirs(csr_dir, exist_ok=True)
+ write_to_file(csr_csv, cpu_interface.get_csr_csv(csr_regions, constants, memory_regions))
def _prepare_software(self):
for name, src_dir in self.software_packages:
subprocess.check_call(["make", "-C", dst_dir, "-f", makefile])
def _initialize_rom(self):
- bios_file = os.path.join(self.output_dir, "software", "bios",
- "bios.bin")
- endianness = cpu_interface.cpu_endianness[self.soc.cpu_type]
- with open(bios_file, "rb") as boot_file:
- boot_data = []
- while True:
- w = boot_file.read(4)
- if not w:
- break
- if endianness == 'little':
- boot_data.append(struct.unpack("<I", w)[0])
- else:
- boot_data.append(struct.unpack(">I", w)[0])
- self.soc.initialize_rom(boot_data)
+ bios_file = os.path.join(self.output_dir, "software", "bios","bios.bin")
+ bios_data = soc_core.get_mem_data(bios_file, self.soc.cpu.endianness)
+ self.soc.initialize_rom(bios_data)
def build(self, toolchain_path=None, **kwargs):
self.soc.finalize()
if not self.soc.integrated_rom_initialized:
self._initialize_rom()
- if self.csr_csv is not None:
- self._generate_csr_csv()
+ self._generate_csr_map(self.csr_json, self.csr_csv)
if self.gateware_toolchain_path is not None:
toolchain_path = self.gateware_toolchain_path
parser.add_argument("--csr-csv", default=None,
help="store CSR map in CSV format into the "
"specified file")
+ parser.add_argument("--csr-json", default=None,
+ help="store CSR map in JSON format into the "
+ "specified file")
def builder_argdict(args):
projects / litex.git / blobdiff