self.logger.error(str(self.io_regions[overlap[0]]))
self.logger.error(str(self.io_regions[overlap[1]]))
raise
- self.logger.info("{} Region {} {}.".format(
+ self.logger.info("{} Region {} at {}.".format(
colorer(name, color="underline"),
colorer("added", color="green"),
str(region)))
self.logger.error(str(self.regions[overlap[0]]))
self.logger.error(str(self.regions[overlap[1]]))
raise
- self.logger.info("{} Region {} {}.".format(
+ self.logger.info("{} Region {} at {}.".format(
colorer(name, color="underline"),
colorer("allocated" if allocated else "added", color="cyan" if allocated else "green"),
str(region)))
def __str__(self):
r = "{} Locations: ({})\n".format(self.name, len(self.locs.keys())) if len(self.locs.keys()) else ""
locs = {k: v for k, v in sorted(self.locs.items(), key=lambda item: item[1])}
+ length = 0
for name in locs.keys():
- r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(20-len(name)), colorer(self.locs[name]))
+ if len(name) > length: length = len(name)
+ for name in locs.keys():
+ r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(length + 1 - len(name)), colorer(self.locs[name]))
return r
# SoCCSRHandler ------------------------------------------------------------------------------------
# SoC CSR Interconnect ---------------------------------------------------------------------
self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
- address_map = self.csr.address_map,
- data_width = self.csr.data_width,
- address_width = self.csr.address_width,
- alignment = self.csr.alignment,
- paging = self.csr.paging,
- )
+ address_map = self.csr.address_map,
+ data_width = self.csr.data_width,
+ address_width = self.csr.address_width,
+ alignment = self.csr.alignment,
+ paging = self.csr.paging,
+ soc_bus_data_width = self.bus.data_width)
if len(self.csr.masters):
self.submodules.csr_interconnect = csr_bus.InterconnectShared(
masters = list(self.csr.masters.values()),
self.add_config("L2_SIZE", l2_cache_size)
# Wishbone Slave <--> LiteDRAM bridge --------------------------------------------------
- self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port)
+ self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port,
+ base_address = self.bus.regions["main_ram"].origin)