integration/soc: -x on soc.py

[litex.git] / litex / soc / integration / soc.py

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
old mode 100755 (executable)
new mode 100644 (file)
index 91c3306..df1e1e1
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -171,7 +171,7 @@ class SoCBusHandler(Module):
                 self.logger.error(str(self.io_regions[overlap[0]]))
                 self.logger.error(str(self.io_regions[overlap[1]]))
                 raise
-            self.logger.info("{} Region {} {}.".format(
+            self.logger.info("{} Region {} at {}.".format(
                 colorer(name,    color="underline"),
                 colorer("added", color="green"),
                 str(region)))
@@ -202,7 +202,7 @@ class SoCBusHandler(Module):
                     self.logger.error(str(self.regions[overlap[0]]))
                     self.logger.error(str(self.regions[overlap[1]]))
                     raise
-            self.logger.info("{} Region {} {}.".format(
+            self.logger.info("{} Region {} at {}.".format(
                 colorer(name, color="underline"),
                 colorer("allocated" if allocated else "added", color="cyan" if allocated else "green"),
                 str(region)))
@@ -418,8 +418,11 @@ class SoCLocHandler(Module):
     def __str__(self):
         r = "{} Locations: ({})\n".format(self.name, len(self.locs.keys())) if len(self.locs.keys()) else ""
         locs = {k: v for k, v in sorted(self.locs.items(), key=lambda item: item[1])}
+        length = 0
         for name in locs.keys():
-           r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(20-len(name)), colorer(self.locs[name]))
+            if len(name) > length: length = len(name)
+        for name in locs.keys():
+           r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(length + 1 - len(name)), colorer(self.locs[name]))
         return r
 
 # SoCCSRHandler ------------------------------------------------------------------------------------
@@ -811,12 +814,12 @@ class SoC(Module):
 
         # SoC CSR Interconnect ---------------------------------------------------------------------
         self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
-            address_map   = self.csr.address_map,
-            data_width    = self.csr.data_width,
-            address_width = self.csr.address_width,
-            alignment     = self.csr.alignment,
-            paging        = self.csr.paging,
-        )
+            address_map        = self.csr.address_map,
+            data_width         = self.csr.data_width,
+            address_width      = self.csr.address_width,
+            alignment          = self.csr.alignment,
+            paging             = self.csr.paging,
+            soc_bus_data_width = self.bus.data_width)
         if len(self.csr.masters):
             self.submodules.csr_interconnect = csr_bus.InterconnectShared(
                 masters = list(self.csr.masters.values()),
@@ -1001,4 +1004,5 @@ class LiteXSoC(SoC):
             self.add_config("L2_SIZE", l2_cache_size)
 
             # Wishbone Slave <--> LiteDRAM bridge --------------------------------------------------
-            self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port)
+            self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port,
+                base_address = self.bus.regions["main_ram"].origin)