from litedram.core import LiteDRAMCore
from litedram.frontend.wishbone import LiteDRAMWishbone2Native
+from litedram.frontend.axi import LiteDRAMAXI2Native
# TODO:
# - replace raise with exit on logging error.
-# - add configurable CSR paging.
# - cleanup SoCCSRRegion
logging.basicConfig(level=logging.INFO)
self.logger.error(str(self.io_regions[overlap[0]]))
self.logger.error(str(self.io_regions[overlap[1]]))
raise
- self.logger.info("{} Region {} {}.".format(
+ self.logger.info("{} Region {} at {}.".format(
colorer(name, color="underline"),
colorer("added", color="green"),
str(region)))
self.logger.error(str(self.regions[overlap[0]]))
self.logger.error(str(self.regions[overlap[1]]))
raise
- self.logger.info("{} Region {} {}.".format(
+ self.logger.info("{} Region {} at {}.".format(
colorer(name, color="underline"),
colorer("allocated" if allocated else "added", color="cyan" if allocated else "green"),
str(region)))
def __str__(self):
r = "{} Locations: ({})\n".format(self.name, len(self.locs.keys())) if len(self.locs.keys()) else ""
locs = {k: v for k, v in sorted(self.locs.items(), key=lambda item: item[1])}
+ length = 0
for name in locs.keys():
- r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(20-len(name)), colorer(self.locs[name]))
+ if len(name) > length: length = len(name)
+ for name in locs.keys():
+ r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(length + 1 - len(name)), colorer(self.locs[name]))
return r
# SoCCSRHandler ------------------------------------------------------------------------------------
class SoCCSRHandler(SoCLocHandler):
supported_data_width = [8, 32]
- supported_address_width = [14, 15]
+ supported_address_width = [14+i for i in range(4)]
supported_alignment = [32, 64]
- supported_paging = [0x800]
+ supported_paging = [0x800*2**i for i in range(4)]
# Creation -------------------------------------------------------------------------------------
def __init__(self, data_width=32, address_width=14, alignment=32, paging=0x800, reserved_csrs={}):
- SoCLocHandler.__init__(self, "CSR", n_locs=4*2**address_width//paging) # FIXME
+ SoCLocHandler.__init__(self, "CSR", n_locs=alignment//8*(2**address_width)//paging)
self.logger = logging.getLogger("SoCCSRHandler")
self.logger.info("Creating CSR Handler...")
# Check Paging
if paging not in self.supported_paging:
- self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
+ self.logger.error("Unsupported {} 0x{}, supporteds: {:s}".format(
colorer("Paging", color="red"),
- colorer(paging),
- colorer(", ".join(str(x) for x in self.supported_paging))))
+ colorer("{:x}".format(paging)),
+ colorer(", ".join("0x{:x}".format(x) for x in self.supported_paging))))
raise
# Create CSR Handler
self.paging = paging
self.masters = {}
self.regions = {}
- self.logger.info("{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).".format(
+ self.logger.info("{}-bit CSR Bus, {}-bit Aligned, {}KiB Address Space, {}B Paging (Up to {} Locations).".format(
colorer(self.data_width),
+ colorer(self.alignment),
colorer(2**self.address_width/2**10),
colorer(self.paging),
colorer(self.n_locs)))
self.logger.info("CSR Handler {}.".format(colorer("created", color="green")))
+ # Update CSR Alignment ----------------------------------------------------------------------------
+ def update_alignment(self, alignment):
+ # Check Alignment
+ if alignment not in self.supported_alignment:
+ self.logger.error("Unsupported {}: {} supporteds: {:s}".format(
+ colorer("Alignment", color="red"),
+ colorer(alignment),
+ colorer(", ".join(str(x) for x in self.supported_alignment))))
+ raise
+ self.logger.info("Alignment {} from {}-bit to {}-bit.".format(
+ colorer("updated", color="cyan"),
+ colorer(self.alignment),
+ colorer(alignment)))
+ self.alignment = alignment
+
# Add Master -----------------------------------------------------------------------------------
def add_master(self, name=None, master=None):
if name is None:
# Str ------------------------------------------------------------------------------------------
def __str__(self):
- r = "{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
+ r = "{}-bit CSR Bus, {}-bit Aligned, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
colorer(self.data_width),
+ colorer(self.alignment),
colorer(2**self.address_width/2**10),
colorer(self.paging),
colorer(self.n_locs))
# SoC ----------------------------------------------------------------------------------------------
class SoC(Module):
+ mem_map = {}
def __init__(self, platform, sys_clk_freq,
bus_standard = "wishbone",
for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))
self.mem_map.update(self.cpu.mem_map) # FIXME
+ self.csr.update_alignment(self.cpu.data_width)
# Add Bus Masters/CSR/IRQs
if not isinstance(self.cpu, cpu.CPUNone):
if reset_address is None:
self.cpu.set_reset_address(reset_address)
for n, cpu_bus in enumerate(self.cpu.buses):
self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
- self.add_csr("cpu", use_loc_if_exists=True)
+ self.csr.add("cpu", use_loc_if_exists=True)
for name, loc in self.cpu.interrupts.items():
self.irq.add(name, loc)
if hasattr(self, "ctrl"):
# SoC CSR Interconnect ---------------------------------------------------------------------
self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
- address_map = self.csr.address_map,
- data_width = self.csr.data_width,
- address_width = self.csr.address_width,
- alignment = self.csr.alignment
- )
+ address_map = self.csr.address_map,
+ data_width = self.csr.data_width,
+ address_width = self.csr.address_width,
+ alignment = self.csr.alignment,
+ paging = self.csr.paging,
+ soc_bus_data_width = self.bus.data_width)
if len(self.csr.masters):
self.submodules.csr_interconnect = csr_bus.InterconnectShared(
masters = list(self.csr.masters.values()),
self.check_if_exists(name)
if with_build_time:
identifier += " " + build_time()
- setattr(self.submodules, name, Identifier(ident))
+ setattr(self.submodules, name, Identifier(identifier))
self.csr.add(name + "_mem", use_loc_if_exists=True)
# Add UART -------------------------------------------------------------------------------------
self.add_config("L2_SIZE", l2_cache_size)
# Wishbone Slave <--> LiteDRAM bridge --------------------------------------------------
- self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port)
+ self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port,
+ base_address = self.bus.regions["main_ram"].origin)
projects / litex.git / blobdiff