soc/integration/csr_bridge: use registered version only when SDRAM is present.

[litex.git] / litex / soc / integration / soc_core.py

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 281f34e4e12723d054e6a2fae2aa3e525774ab2b..6074132225ed1dcd4c7438fe327aada32d8e3939 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -187,9 +187,6 @@ class SoCCore(LiteXSoC):
             if timer_uptime:
                 self.timer0.add_uptime()
 
-        # Add CSR bridge
-        self.add_csr_bridge(self.mem_map["csr"])
-
     # Methods --------------------------------------------------------------------------------------
 
     def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False):