sdram/phy/s6ddrphy: add DDR3 support

[litex.git] / make.py

diff --git a/make.py b/make.py
index 087466ba94a6277be6964c3c1049ceafd99f6382..61ed5fd578afce4fe39f5f11394485dda01d6ba9 100755 (executable)
--- a/make.py
+++ b/make.py
@@ -1,6 +1,10 @@
 #!/usr/bin/env python3
 
-import sys, os, argparse, subprocess, struct
+import sys
+import os
+import argparse
+import subprocess
+import struct
 
 from mibuild.tools import write_to_file
 from migen.util.misc import autotype
@@ -60,7 +64,7 @@ if __name__ == "__main__":
     if args.external:
         external_target = os.path.join(args.external, "targets")
         external_platform = os.path.join(args.external, "platforms")
-        sys.path.insert(1, os.path.abspath(args.external))
+        sys.path.insert(0, os.path.abspath(args.external))
 
     # create top-level SoC object
     target_module = misoc_import("targets", external_target, args.target)