#!/usr/bin/env python3
-import argparse, os, importlib, subprocess
+import sys
+import os
+import argparse
+import subprocess
+import struct
from mibuild.tools import write_to_file
+from migen.util.misc import autotype
+from migen.fhdl import simplify
-from milkymist import cif
-import top, jtag
+from misoclib.soc import cpuif
+from misoclib.mem.sdram.phy import initsequence
-def build(platform_name, build_bitstream, build_header, *soc_args, **soc_kwargs):
- platform_module = importlib.import_module("mibuild.platforms."+platform_name)
- platform = platform_module.Platform()
- soc = top.SoC(platform, platform_name, *soc_args, **soc_kwargs)
-
- platform.add_platform_command("""
-INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
-INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
+from misoc_import import misoc_import
-PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
-PIN "pix2x_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
+
+def _get_args():
+ parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
+ description="""\
+MiSoC - a high performance and small footprint SoC based on Migen.
+
+This program builds and/or loads MiSoC components.
+One or several actions can be specified:
+
+clean delete previous build(s).
+build-bitstream build FPGA bitstream. Implies build-bios on targets with
+ integrated BIOS.
+build-headers build software header files with CPU/CSR/IRQ/SDRAM_PHY definitions.
+build-csr-csv save CSR map into CSV file.
+build-bios build BIOS. Implies build-header.
+
+load-bitstream load bitstream into volatile storage.
+flash-bitstream load bitstream into non-volatile storage.
+flash-bios load BIOS into non-volatile storage.
+
+all clean, build-bitstream, build-bios, flash-bitstream, flash-bios.
+
+Load/flash actions use the existing outputs, and do not trigger new builds.
""")
- if hasattr(soc, "fb"):
- platform.add_platform_command("""
-NET "{vga_clk}" TNM_NET = "GRPvga_clk";
-NET "sys_clk" TNM_NET = "GRPsys_clk";
-TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
-TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
-""", vga_clk=soc.fb.driver.clocking.cd_pix.clk)
-
- for d in ["mxcrg", "minimac3"]:
- platform.add_source_dir(os.path.join("verilog", d))
- platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
- "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
- "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
- "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
- "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
- "lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
- "jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
- platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
-
- if build_bitstream:
- build_name = "soc-"+platform_name
- platform.build(soc, build_name=build_name)
- subprocess.call(["tools/byteswap", "build/"+build_name+".bin", "build/"+build_name+".fpg"])
- else:
- soc.finalize()
- if build_header:
- csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
- write_to_file("software/include/hw/csr.h", csr_header)
-
- sdram_phy_header = cif.get_sdram_phy_header(soc.ddrphy)
- write_to_file("software/include/hw/sdram_phy.h", sdram_phy_header)
-
-
-def main():
- parser = argparse.ArgumentParser(description="milkymist-ng - a high performance SoC built on Migen technology.")
- parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
- parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
- parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header files with CSR/IRQ/SDRAM_PHY defs")
- parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to SRAM")
- parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
- parser.add_argument("-m", "--with-memtest", default=False, action="store_true", help="include memtest cores")
- args = parser.parse_args()
-
- build(args.platform, not args.no_bitstream, not args.no_header, args.with_memtest)
- if args.load:
- jtag.load("build/soc-"+args.platform+".bit")
- if args.flash:
- jtag.flash("build/soc-"+args.platform+".fpg")
+ parser.add_argument("-t", "--target", default="mlabs_video", help="SoC type to build")
+ parser.add_argument("-s", "--sub-target", default="", help="variant of the SoC type to build")
+ parser.add_argument("-p", "--platform", default=None, help="platform to build for")
+ parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
+ parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
+ parser.add_argument("-X", "--external", default="", help="use external directory for targets, platforms and imports")
+ parser.add_argument("--csr_csv", default="csr.csv", help="CSV file to save the CSR map into")
+
+ parser.add_argument("-d", "--decorate", default=[], action="append", help="apply simplification decorator to top-level")
+ parser.add_argument("-Ob", "--build-option", default=[], nargs=2, action="append", help="set build option")
+ parser.add_argument("-f", "--flash-proxy-dir", default=None, help="set search directory for flash proxy bitstreams")
+
+ parser.add_argument("action", nargs="+", help="specify an action")
+
+ return parser.parse_args()
if __name__ == "__main__":
- main()
+ args = _get_args()
+
+ external_target = ""
+ external_platform = ""
+ if args.external:
+ external_target = os.path.join(args.external, "targets")
+ external_platform = os.path.join(args.external, "platforms")
+ sys.path.insert(0, os.path.abspath(args.external))
+
+ # create top-level SoC object
+ target_module = misoc_import("targets", external_target, args.target)
+ if args.sub_target:
+ top_class = getattr(target_module, args.sub_target)
+ else:
+ top_class = target_module.default_subtarget
+
+ if args.platform is None:
+ if hasattr(top_class, "default_platform"):
+ platform_name = top_class.default_platform
+ else:
+ raise ValueError("Target has no default platform, specify a platform with -p your_platform")
+ else:
+ platform_name = args.platform
+ platform_module = misoc_import("mibuild.platforms", external_platform, platform_name)
+ platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
+ platform = platform_module.Platform(**platform_kwargs)
+ if args.external:
+ platform.soc_ext_path = os.path.abspath(args.external)
+
+ build_name = args.target + "-" + top_class.__name__.lower() + "-" + platform_name
+ top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
+ soc = top_class(platform, **top_kwargs)
+ soc.finalize()
+ memory_regions = soc.get_memory_regions()
+ csr_regions = soc.get_csr_regions()
+
+ # decode actions
+ action_list = ["clean", "build-bitstream", "build-headers", "build-csr-csv", "build-bios",
+ "load-bitstream", "flash-bitstream", "flash-bios", "all"]
+ actions = {k: False for k in action_list}
+ for action in args.action:
+ if action in actions:
+ actions[action] = True
+ else:
+ print("Unknown action: {}. Valid actions are:".format(action))
+ for a in action_list:
+ print(" "+a)
+ sys.exit(1)
+
+ print("""\
+ __ ___ _ ____ _____
+ / |/ / (_) / __/__ / ___/
+ / /|_/ / / / _\ \/ _ \/ /__
+ /_/ /_/ /_/ /___/\___/\___/
+
+a high performance and small footprint SoC based on Migen
+
+====== Building for: ======
+Platform: {}
+Target: {}
+Subtarget: {}
+CPU type: {}
+===========================""".format(platform_name, args.target, top_class.__name__, soc.cpu_type))
+
+ # dependencies
+ if actions["all"]:
+ actions["clean"] = True
+ actions["build-bitstream"] = True
+ actions["build-bios"] = True
+ if not actions["load-bitstream"]:
+ actions["flash-bitstream"] = True
+ if not soc.integrated_rom_size:
+ actions["flash-bios"] = True
+ if actions["build-bitstream"] and soc.integrated_rom_size:
+ actions["build-bios"] = True
+ if actions["build-bios"]:
+ actions["build-headers"] = True
+
+ if actions["clean"]:
+ subprocess.check_call("rm -rvf build/*", shell=True) # Need shell for the build/* globbing
+ subprocess.check_call(["make", "-C", os.path.join("software", "libcompiler-rt"), "clean"])
+ subprocess.check_call(["make", "-C", os.path.join("software", "libbase"), "clean"])
+ subprocess.check_call(["make", "-C", os.path.join("software", "libnet"), "clean"])
+ subprocess.check_call(["make", "-C", os.path.join("software", "bios"), "clean"])
+
+ if actions["build-headers"]:
+ boilerplate = """/*
+ * Platform: {}
+ * Target: {}
+ * Subtarget: {}
+ * CPU type: {}
+ */
+
+""".format(platform_name, args.target, top_class.__name__, soc.cpu_type)
+ genhdir = os.path.join("software", "include", "generated")
+ if soc.cpu_type != "none":
+ cpu_mak = cpuif.get_cpu_mak(soc.cpu_type)
+ write_to_file(os.path.join(genhdir, "cpu.mak"), cpu_mak)
+ linker_output_format = cpuif.get_linker_output_format(soc.cpu_type)
+ write_to_file(os.path.join(genhdir, "output_format.ld"), linker_output_format)
+
+ linker_regions = cpuif.get_linker_regions(memory_regions)
+ write_to_file(os.path.join(genhdir, "regions.ld"), boilerplate + linker_regions)
+
+ for sdram_phy in ["sdrphy", "ddrphy"]:
+ if hasattr(soc, sdram_phy):
+ sdram_phy_header = initsequence.get_sdram_phy_header(getattr(soc, sdram_phy).settings)
+ write_to_file(os.path.join(genhdir, "sdram_phy.h"), boilerplate + sdram_phy_header)
+ mem_header = cpuif.get_mem_header(memory_regions, getattr(soc, "flash_boot_address", None))
+ write_to_file(os.path.join(genhdir, "mem.h"), boilerplate + mem_header)
+ csr_header = cpuif.get_csr_header(csr_regions, soc.get_constants())
+ write_to_file(os.path.join(genhdir, "csr.h"), boilerplate + csr_header)
+
+ if actions["build-csr-csv"]:
+ csr_csv = cpuif.get_csr_csv(csr_regions)
+ write_to_file(args.csr_csv, csr_csv)
+
+ if actions["build-bios"]:
+ ret = subprocess.call(["make", "-C", os.path.join("software", "bios")])
+ if ret:
+ raise OSError("BIOS build failed")
+
+ bios_file = os.path.join("software", "bios", "bios.bin")
+
+ if actions["build-bitstream"]:
+ if soc.integrated_rom_size:
+ with open(bios_file, "rb") as boot_file:
+ boot_data = []
+ while True:
+ w = boot_file.read(4)
+ if not w:
+ break
+ boot_data.append(struct.unpack(">I", w)[0])
+ soc.init_rom(boot_data)
+
+ for decorator in args.decorate:
+ soc = getattr(simplify, decorator)(soc)
+ build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
+ vns = platform.build(soc, build_name=build_name, **build_kwargs)
+ soc.do_exit(vns)
+
+ if actions["load-bitstream"]:
+ prog = platform.create_programmer()
+ prog.load_bitstream(os.path.join("build", build_name + platform.bitstream_ext))
+
+ if actions["flash-bitstream"]:
+ prog = platform.create_programmer()
+ prog.set_flash_proxy_dir(args.flash_proxy_dir)
+ if prog.needs_bitreverse:
+ flashbit = os.path.join("build", build_name + ".fpg")
+ subprocess.check_call([os.path.join("tools", "byteswap"),
+ os.path.join("build", build_name + ".bin"),
+ flashbit])
+ else:
+ flashbit = os.path.join("build", build_name + ".bin")
+ prog.flash(0, flashbit)
+
+ if actions["flash-bios"]:
+ prog = platform.create_programmer()
+ prog.set_flash_proxy_dir(args.flash_proxy_dir)
+ prog.flash(soc.cpu_reset_address, bios_file)
projects / litex.git / blobdiff