from migen.bus.asmibus import *
from migen.corelogic.roundrobin import *
from migen.corelogic.fsm import FSM
-from migen.corelogic.misc import multimux, optree
+from migen.corelogic.misc import optree
from milkymist.asmicon.multiplexer import *
if isinstance(address, int):
return (address & (2**self._b1 - 1)) << self.address_align
else:
- return Cat(Constant(0, BV(self.address_align)), address[:self._b1])
+ return Cat(Replicate(0, self.address_align), address[:self._b1])
class _Selector:
def __init__(self, slicer, bankn, slots):
self.nslots = len(self.slots)
self.stb = Signal()
self.ack = Signal()
- self.tag = Signal(BV(bits_for(self.nslots-1)))
- self.adr = Signal(self.slots[0].adr.bv)
+ self.tag = Signal(max=self.nslots)
+ self.adr = Signal(self.slots[0].adr.nbits)
self.we = Signal()
+ # derived classes should drive rr.request
+ self.rr = RoundRobin(self.nslots, SP_CE)
+
+ def get_fragment(self):
+ comb = []
+ rr = self.rr
+
+ # Multiplex
+ state = Signal(2)
+ comb += [
+ state.eq(Array(slot.state for slot in self.slots)[rr.grant]),
+ self.adr.eq(Array(slot.adr for slot in self.slots)[rr.grant]),
+ self.we.eq(Array(slot.we for slot in self.slots)[rr.grant]),
+ self.stb.eq(
+ (self.slicer.bank(self.adr) == self.bankn) \
+ & (state == SLOT_PENDING)),
+ rr.ce.eq(self.ack | ~self.stb),
+ self.tag.eq(rr.grant)
+ ]
+ comb += [If((rr.grant == i) & self.stb & self.ack, slot.process.eq(1))
+ for i, slot in enumerate(self.slots)]
+
+ return Fragment(comb) + rr.get_fragment()
+
+class _SimpleSelector(_Selector):
+ def get_fragment(self):
+ comb = []
+ for i, slot in enumerate(self.slots):
+ comb.append(self.rr.request[i].eq(
+ (self.slicer.bank(slot.adr) == self.bankn) & \
+ (slot.state == SLOT_PENDING)
+ ))
+
+ return Fragment(comb) + super().get_fragment()
+
+class _FullSelector(_Selector):
def get_fragment(self):
comb = []
sync = []
+ rr = self.rr
# List outstanding requests for our bank
outstandings = []
outstandings.append(outstanding)
# Row tracking
- openrow_r = Signal(BV(self.slicer.geom_settings.row_a))
- openrow_n = Signal(BV(self.slicer.geom_settings.row_a))
- openrow = Signal(BV(self.slicer.geom_settings.row_a))
+ openrow_r = Signal(self.slicer.geom_settings.row_a)
+ openrow_n = Signal(self.slicer.geom_settings.row_a)
+ openrow = Signal(self.slicer.geom_settings.row_a)
comb += [
openrow_n.eq(self.slicer.row(self.adr)),
If(self.stb,
select_stmt = If(has_mature, *best_mature).Else(select_stmt)
comb.append(select_stmt)
- # Multiplex
- state = Signal(BV(2))
- mux_outputs = [state, self.adr, self.we]
- mux_inputs = [[slot.state, slot.adr, slot.we]
- for slot in self.slots]
- comb += multimux(rr.grant, mux_inputs, mux_outputs)
- comb += [
- self.stb.eq(
- (self.slicer.bank(self.adr) == self.bankn) \
- & (state == SLOT_PENDING)),
- rr.ce.eq(self.ack),
- self.tag.eq(rr.grant)
- ]
- comb += [If((rr.grant == i) & self.stb & self.ack, slot.process.eq(1))
- for i, slot in enumerate(self.slots)]
-
- return Fragment(comb, sync) + rr.get_fragment()
+ return Fragment(comb, sync) + super().get_fragment()
class _Buffer:
def __init__(self, source):
return Fragment(comb, sync)
class BankMachine:
- def __init__(self, geom_settings, timing_settings, address_align, bankn, slots):
+ def __init__(self, geom_settings, timing_settings, address_align, bankn, slots, full_selector):
self.geom_settings = geom_settings
self.timing_settings = timing_settings
self.address_align = address_align
self.bankn = bankn
self.slots = slots
+ self.full_selector = full_selector
self.refresh_req = Signal()
self.refresh_gnt = Signal()
# Sub components
slicer = _AddressSlicer(self.geom_settings, self.address_align)
- selector = _Selector(slicer, self.bankn, self.slots)
- buf = _Buffer(selector)
+ if self.full_selector:
+ selector = _FullSelector(slicer, self.bankn, self.slots)
+ buf = _Buffer(selector)
+ cmdsource = buf
+ else:
+ selector = _SimpleSelector(slicer, self.bankn, self.slots)
+ cmdsource = selector
# Row tracking
has_openrow = Signal()
- openrow = Signal(BV(self.geom_settings.row_a))
+ openrow = Signal(self.geom_settings.row_a)
hit = Signal()
- comb.append(hit.eq(openrow == slicer.row(buf.adr)))
+ comb.append(hit.eq(openrow == slicer.row(cmdsource.adr)))
track_open = Signal()
track_close = Signal()
sync += [
If(track_open,
has_openrow.eq(1),
- openrow.eq(slicer.row(buf.adr))
+ openrow.eq(slicer.row(cmdsource.adr))
),
If(track_close,
has_openrow.eq(0)
comb += [
self.cmd.ba.eq(self.bankn),
If(s_row_adr,
- self.cmd.a.eq(slicer.row(buf.adr))
+ self.cmd.a.eq(slicer.row(cmdsource.adr))
).Else(
- self.cmd.a.eq(slicer.col(buf.adr))
+ self.cmd.a.eq(slicer.col(cmdsource.adr))
)
]
- comb.append(self.cmd.tag.eq(buf.tag))
+ comb.append(self.cmd.tag.eq(cmdsource.tag))
+
+ # Respect write-to-precharge specification
+ precharge_ok = Signal()
+ t_unsafe_precharge = 2 + self.timing_settings.tWR - 1
+ unsafe_precharge_count = Signal(max=t_unsafe_precharge+1)
+ comb.append(precharge_ok.eq(unsafe_precharge_count == 0))
+ sync += [
+ If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,
+ unsafe_precharge_count.eq(t_unsafe_precharge)
+ ).Elif(~precharge_ok,
+ unsafe_precharge_count.eq(unsafe_precharge_count-1)
+ )
+ ]
# Control and command generation FSM
fsm = FSM("REGULAR", "PRECHARGE", "ACTIVATE", "REFRESH", delayed_enters=[
fsm.act(fsm.REGULAR,
If(self.refresh_req,
fsm.next_state(fsm.REFRESH)
- ).Elif(buf.stb,
+ ).Elif(cmdsource.stb,
If(has_openrow,
If(hit,
+ # NB: write-to-read specification is enforced by multiplexer
self.cmd.stb.eq(1),
- buf.ack.eq(self.cmd.ack),
- self.cmd.is_read.eq(~buf.we),
- self.cmd.is_write.eq(buf.we),
+ cmdsource.ack.eq(self.cmd.ack),
+ self.cmd.is_read.eq(~cmdsource.we),
+ self.cmd.is_write.eq(cmdsource.we),
self.cmd.cas_n.eq(0),
- self.cmd.we_n.eq(~buf.we)
+ self.cmd.we_n.eq(~cmdsource.we)
).Else(
fsm.next_state(fsm.PRECHARGE)
)
# 1. we are presenting the column address, A10 is always low
# 2. since we always go to the ACTIVATE state, we do not need
# to assert track_close.
- self.cmd.stb.eq(1),
- If(self.cmd.ack, fsm.next_state(fsm.TRP)),
- self.cmd.ras_n.eq(0),
- self.cmd.we_n.eq(0)
+ If(precharge_ok,
+ self.cmd.stb.eq(1),
+ If(self.cmd.ack, fsm.next_state(fsm.TRP)),
+ self.cmd.ras_n.eq(0),
+ self.cmd.we_n.eq(0)
+ )
)
fsm.act(fsm.ACTIVATE,
s_row_adr.eq(1),
self.cmd.ras_n.eq(0)
)
fsm.act(fsm.REFRESH,
- self.refresh_gnt.eq(1),
+ self.refresh_gnt.eq(precharge_ok),
track_close.eq(1),
If(~self.refresh_req, fsm.next_state(fsm.REGULAR))
)
+ if self.full_selector:
+ buf_fragment = buf.get_fragment()
+ else:
+ buf_fragment = Fragment()
return Fragment(comb, sync) + \
selector.get_fragment() + \
- buf.get_fragment() + \
+ buf_fragment + \
fsm.get_fragment()
projects / litex.git / blobdiff