Replace Signal(bits_for(... with Signal(max=...

[litex.git] / milkymist / asmicon / bankmachine.py

diff --git a/milkymist/asmicon/bankmachine.py b/milkymist/asmicon/bankmachine.py
index ead10ca3cddbf864d785311c790370cde7af69ca..8b17408111ad88c2d6244463c0e5d713b45c20a5 100644 (file)
--- a/milkymist/asmicon/bankmachine.py
+++ b/milkymist/asmicon/bankmachine.py
@@ -31,7 +31,7 @@ class _AddressSlicer:
                if isinstance(address, int):
                        return (address & (2**self._b1 - 1)) << self.address_align
                else:
-                       return Cat(Constant(0, BV(self.address_align)), address[:self._b1])
+                       return Cat(Replicate(0, self.address_align), address[:self._b1])
 
 class _Selector:
        def __init__(self, slicer, bankn, slots):
@@ -42,8 +42,8 @@ class _Selector:
                self.nslots = len(self.slots)
                self.stb = Signal()
                self.ack = Signal()
-               self.tag = Signal(BV(bits_for(self.nslots-1)))
-               self.adr = Signal(self.slots[0].adr.bv)
+               self.tag = Signal(max=self.nslots)
+               self.adr = Signal(self.slots[0].adr.nbits)
                self.we = Signal()
                
                # derived classes should drive rr.request
@@ -54,7 +54,7 @@ class _Selector:
                rr = self.rr
                
                # Multiplex
-               state = Signal(BV(2))
+               state = Signal(2)
                comb += [
                        state.eq(Array(slot.state for slot in self.slots)[rr.grant]),
                        self.adr.eq(Array(slot.adr for slot in self.slots)[rr.grant]),
@@ -98,9 +98,9 @@ class _FullSelector(_Selector):
                        outstandings.append(outstanding)
                
                # Row tracking
-               openrow_r = Signal(BV(self.slicer.geom_settings.row_a))
-               openrow_n = Signal(BV(self.slicer.geom_settings.row_a))
-               openrow = Signal(BV(self.slicer.geom_settings.row_a))
+               openrow_r = Signal(self.slicer.geom_settings.row_a)
+               openrow_n = Signal(self.slicer.geom_settings.row_a)
+               openrow = Signal(self.slicer.geom_settings.row_a)
                comb += [
                        openrow_n.eq(self.slicer.row(self.adr)),
                        If(self.stb,
@@ -207,7 +207,7 @@ class BankMachine:
                
                # Row tracking
                has_openrow = Signal()
-               openrow = Signal(BV(self.geom_settings.row_a))
+               openrow = Signal(self.geom_settings.row_a)
                hit = Signal()
                comb.append(hit.eq(openrow == slicer.row(cmdsource.adr)))
                track_open = Signal()
@@ -235,6 +235,19 @@ class BankMachine:
                
                comb.append(self.cmd.tag.eq(cmdsource.tag))
                
+               # Respect write-to-precharge specification
+               precharge_ok = Signal()
+               t_unsafe_precharge = 2 + self.timing_settings.tWR - 1
+               unsafe_precharge_count = Signal(max=t_unsafe_precharge+1)
+               comb.append(precharge_ok.eq(unsafe_precharge_count == 0))
+               sync += [
+                       If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,
+                               unsafe_precharge_count.eq(t_unsafe_precharge)
+                       ).Elif(~precharge_ok,
+                               unsafe_precharge_count.eq(unsafe_precharge_count-1)
+                       )
+               ]
+               
                # Control and command generation FSM
                fsm = FSM("REGULAR", "PRECHARGE", "ACTIVATE", "REFRESH", delayed_enters=[
                        ("TRP", "ACTIVATE", self.timing_settings.tRP-1),
@@ -246,6 +259,7 @@ class BankMachine:
                        ).Elif(cmdsource.stb,
                                If(has_openrow,
                                        If(hit,
+                                               # NB: write-to-read specification is enforced by multiplexer
                                                self.cmd.stb.eq(1),
                                                cmdsource.ack.eq(self.cmd.ack),
                                                self.cmd.is_read.eq(~cmdsource.we),
@@ -265,10 +279,12 @@ class BankMachine:
                        # 1. we are presenting the column address, A10 is always low
                        # 2. since we always go to the ACTIVATE state, we do not need
                        # to assert track_close.
-                       self.cmd.stb.eq(1),
-                       If(self.cmd.ack, fsm.next_state(fsm.TRP)),
-                       self.cmd.ras_n.eq(0),
-                       self.cmd.we_n.eq(0)
+                       If(precharge_ok,
+                               self.cmd.stb.eq(1),
+                               If(self.cmd.ack, fsm.next_state(fsm.TRP)),
+                               self.cmd.ras_n.eq(0),
+                               self.cmd.we_n.eq(0)
+                       )
                )
                fsm.act(fsm.ACTIVATE,
                        s_row_adr.eq(1),
@@ -278,7 +294,7 @@ class BankMachine:
                        self.cmd.ras_n.eq(0)
                )
                fsm.act(fsm.REFRESH,
-                       self.refresh_gnt.eq(1),
+                       self.refresh_gnt.eq(precharge_ok),
                        track_close.eq(1),
                        If(~self.refresh_req, fsm.next_state(fsm.REGULAR))
                )