-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.flow.actor import *
from migen.flow.network import *
-from migen.flow import plumbing
-from migen.actorlib import ala, misc, dma_asmi, structuring
-from migen.bank.description import *
-from migen.bank import csrgen
+from migen.bank.description import CSRStorage, AutoCSR
+from migen.actorlib import dma_lasmi, structuring, sim, spi
-_hbits = 11
-_vbits = 11
+from milkymist.framebuffer.lib import bpp, pixel_layout, dac_layout, FrameInitiator, VTG, FIFO
-_bpp = 32
-_bpc = 10
-_pixel_layout = [
- ("b", BV(_bpc)),
- ("g", BV(_bpc)),
- ("r", BV(_bpc)),
- ("pad", BV(_bpp-3*_bpc))
-]
-
-_bpc_dac = 8
-_dac_layout = [
- ("hsync", BV(1)),
- ("vsync", BV(1)),
- ("b", BV(_bpc_dac)),
- ("g", BV(_bpc_dac)),
- ("r", BV(_bpc_dac))
-]
-
-class _FrameInitiator(Actor):
- def __init__(self, asmi_bits, length_bits, alignment_bits):
- self._alignment_bits = alignment_bits
-
- self._enable = RegisterField("enable")
-
- self._hres = RegisterField("hres", _hbits, reset=640)
- self._hsync_start = RegisterField("hsync_start", _hbits, reset=656)
- self._hsync_end = RegisterField("hsync_end", _hbits, reset=752)
- self._hscan = RegisterField("hscan", _hbits, reset=799)
-
- self._vres = RegisterField("vres", _vbits, reset=480)
- self._vsync_start = RegisterField("vsync_start", _vbits, reset=492)
- self._vsync_end = RegisterField("vsync_end", _vbits, reset=494)
- self._vscan = RegisterField("vscan", _vbits, reset=524)
+class Framebuffer(Module):
+ def __init__(self, pads, lasmim, simulation=False):
+ pack_factor = lasmim.dw//(2*bpp)
+ packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
+
+ fi = FrameInitiator()
+ dma = spi.DMAReadController(dma_lasmi.Reader(lasmim), spi.MODE_EXTERNAL, length_reset=640*480*4)
+ cast = structuring.Cast(lasmim.dw, packed_pixels, reverse_to=True)
+ unpack = structuring.Unpack(pack_factor, pixel_layout)
+ vtg = VTG()
+ if simulation:
+ fifo = sim.SimActor(sim_fifo_gen(), ("dac", Sink, dac_layout))
+ else:
+ fifo = FIFO()
- self._base = RegisterField("base", asmi_bits + self._alignment_bits)
- self._length = RegisterField("length", length_bits + self._alignment_bits, reset=640*480*4)
-
- layout = [
- ("hres", BV(_hbits)),
- ("hsync_start", BV(_hbits)),
- ("hsync_end", BV(_hbits)),
- ("hscan", BV(_hbits)),
- ("vres", BV(_vbits)),
- ("vsync_start", BV(_vbits)),
- ("vsync_end", BV(_vbits)),
- ("vscan", BV(_vbits)),
- ("base", BV(asmi_bits)),
- ("length", BV(length_bits))
- ]
- super().__init__(("frame", Source, layout))
-
- def get_registers(self):
- return [self._enable,
- self._hres, self._hsync_start, self._hsync_end, self._hscan,
- self._vres, self._vsync_start, self._vsync_end, self._vscan,
- self._base, self._length]
-
- def get_fragment(self):
- # TODO: make address updates atomic
- token = self.token("frame")
- comb = [
- self.busy.eq(0),
- self.endpoints["frame"].stb.eq(self._enable.field.r),
- token.hres.eq(self._hres.field.r),
- token.hsync_start.eq(self._hsync_start.field.r),
- token.hsync_end.eq(self._hsync_end.field.r),
- token.hscan.eq(self._hscan.field.r),
- token.vres.eq(self._vres.field.r),
- token.vsync_start.eq(self._vsync_start.field.r),
- token.vsync_end.eq(self._vsync_end.field.r),
- token.vscan.eq(self._vscan.field.r),
- token.base.eq(self._base.field.r[self._alignment_bits:]),
- token.length.eq(self._length.field.r[self._alignment_bits:])
- ]
- return Fragment(comb)
+ g = DataFlowGraph()
+ g.add_connection(fi, vtg, sink_ep="timing")
+ g.add_connection(dma, cast)
+ g.add_connection(cast, unpack)
+ g.add_connection(unpack, vtg, sink_ep="pixels")
+ g.add_connection(vtg, fifo)
+ self.submodules += CompositeActor(g)
-class VTG(Actor):
- def __init__(self):
- super().__init__(
- ("timing", Sink, [
- ("hres", BV(_hbits)),
- ("hsync_start", BV(_hbits)),
- ("hsync_end", BV(_hbits)),
- ("hscan", BV(_hbits)),
- ("vres", BV(_vbits)),
- ("vsync_start", BV(_vbits)),
- ("vsync_end", BV(_vbits)),
- ("vscan", BV(_vbits))]),
- ("pixels", Sink, _pixel_layout),
- ("dac", Source, _dac_layout)
- )
-
- def get_fragment(self):
- hactive = Signal()
- vactive = Signal()
- active = Signal()
-
- generate_en = Signal()
- hcounter = Signal(BV(_hbits))
- vcounter = Signal(BV(_vbits))
- hsync = Signal()
- vsync = Signal()
-
- comb = [
- active.eq(hactive & vactive),
- If(active,
- self.token("dac").r.eq(self.token("pixels").r[:_bpc_dac]),
- self.token("dac").g.eq(self.token("pixels").g[:_bpc_dac]),
- self.token("dac").b.eq(self.token("pixels").b[:_bpc_dac])
- ),
-
- generate_en.eq(self.endpoints["timing"].stb & self.endpoints["dac"].ack \
- & (~active | self.endpoints["pixels"].stb)),
- self.endpoints["pixels"].ack.eq(self.endpoints["dac"].ack & active),
- self.endpoints["dac"].stb.eq(generate_en)
+ self._enable = CSRStorage()
+ self.comb += [
+ fi.trigger.eq(self._enable.storage),
+ dma.generator.trigger.eq(self._enable.storage),
]
- tp = self.token("timing")
- sync = [
- self.endpoints["timing"].ack.eq(0),
- If(generate_en,
- hcounter.eq(hcounter + 1),
-
- If(hcounter == 0, hactive.eq(1)),
- If(hcounter == tp.hres, hactive.eq(0)),
- If(hcounter == tp.hsync_start, hsync.eq(1)),
- If(hcounter == tp.hsync_end, hsync.eq(0)),
- If(hcounter == tp.hscan,
- hcounter.eq(0),
- If(vcounter == tp.vscan,
- vcounter.eq(0)
+ self._fi = fi
+ self._dma = dma
+
+ # Drive pads
+ if not simulation:
+ self.comb += [
+ pads.hsync_n.eq(fifo.vga_hsync_n),
+ pads.vsync_n.eq(fifo.vga_vsync_n),
+ pads.r.eq(fifo.vga_r),
+ pads.g.eq(fifo.vga_g),
+ pads.b.eq(fifo.vga_b)
+ ]
+ self.comb += pads.psave_n.eq(1)
+
+ def get_csrs(self):
+ return [self._enable] + self._fi.get_csrs() + self._dma.get_csrs()
+
+class Blender(PipelinedActor, AutoCSR):
+ def __init__(self, nimages, latency):
+ self.sink = Sink([("i"+str(i), pixel_layout) for i in range(nimages)])
+ self.source = Source(pixel_layout)
+ factors = []
+ for i in range(nimages):
+ name = "f"+str(i)
+ csr = CSRStorage(8, name=name)
+ setattr(self, name, csr)
+ factors.append(csr.storage)
+ PipelinedActor.__init__(self, latency)
+
+ ###
+
+ imgs = [getattr(self.sink.payload, "i"+str(i)) for i in range(nimages)]
+ outval = Record(pixel_layout)
+ for e in pixel_layout:
+ name = e[0]
+ inpixs = [getattr(img, name) for img in imgs]
+ outpix = getattr(outval, name)
+ for component in ["r", "g", "b"]:
+ incomps = [getattr(pix, component) for pix in inpixs]
+ outcomp = getattr(outpix, component)
+ outcomp_full = Signal(19)
+ self.comb += [
+ outcomp_full.eq(sum(incomp*factor for incomp, factor in zip(incomps, factors))),
+ If(outcomp_full[18],
+ outcomp.eq(2**10 - 1) # saturate on overflow
).Else(
- vcounter.eq(vcounter + 1)
+ outcomp.eq(outcomp_full[8:18])
)
- ),
-
- If(vcounter == 0, vactive.eq(1)),
- If(vcounter == tp.vres, vactive.eq(0)),
- If(vcounter == tp.vsync_start, vsync.eq(1)),
- If(vcounter == tp.vsync_end,
- vsync.eq(0),
- self.endpoints["timing"].ack.eq(1)
- )
- )
- ]
-
- return Fragment(comb, sync)
+ ]
-class FIFO(Actor):
- def __init__(self):
- super().__init__(("dac", Sink, _dac_layout))
-
- self.vga_clk = Signal()
- self.vga_hsync_n = Signal()
- self.vga_vsync_n = Signal()
- self.vga_r = Signal(BV(_bpc_dac))
- self.vga_g = Signal(BV(_bpc_dac))
- self.vga_b = Signal(BV(_bpc_dac))
-
- def get_fragment(self):
- data_width = 2+3*_bpc_dac
- asfifo = Instance("asfifo",
- [
- ("data_out", BV(data_width)),
- ("empty", BV(1)),
-
- ("full", BV(1))
- ], [
- ("read_en", BV(1)),
- ("clk_read", self.vga_clk),
-
- ("data_in", BV(data_width)),
- ("write_en", BV(1)),
-
- ("rst", BV(1))
- ],
- parameters=[
- ("data_width", data_width),
- ("address_width", 8)
- ],
- clkport="clk_write")
- t = self.token("dac")
- return Fragment([
- asfifo.ins["read_en"].eq(1),
-
- self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
- asfifo.ins["write_en"].eq(self.endpoints["dac"].stb),
- asfifo.ins["data_in"].eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
-
- self.busy.eq(0),
- asfifo.ins["rst"].eq(0)
- ], [
- Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"])
- ],
- instances=[asfifo])
+ pipe_stmts = []
+ for i in range(latency):
+ new_outval = Record(pixel_layout)
+ pipe_stmts.append(new_outval.eq(outval))
+ outval = new_outval
+ self.sync += If(self.pipe_ce, pipe_stmts)
+ self.comb += self.source.payload.eq(outval)
+
+class MixFramebuffer(Module, AutoCSR):
+ def __init__(self, pads, *lasmims, blender_latency=5):
+ pack_factor = lasmims[0].dw//(2*bpp)
+ packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
+
+ self._enable = CSRStorage()
+ self.fi = FrameInitiator()
+ self.blender = Blender(len(lasmims), blender_latency)
+ self.comb += self.fi.trigger.eq(self._enable.storage)
-class Framebuffer:
- def __init__(self, address, asmiport):
- asmi_bits = asmiport.hub.aw
- alignment_bits = bits_for(asmiport.hub.dw//8)
- length_bits = _hbits + _vbits + 2 - alignment_bits
- pack_factor = asmiport.hub.dw//_bpp
- packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
-
- fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
- adrloop = ActorNode(misc.IntSequence(length_bits))
- adrbase = ActorNode(ala.Add(BV(asmi_bits)))
- adrbuffer = ActorNode(plumbing.Buffer)
- dma = ActorNode(dma_asmi.SequentialReader(asmiport))
- cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
- unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
- vtg = ActorNode(VTG())
- fifo = ActorNode(FIFO())
-
g = DataFlowGraph()
- g.add_connection(fi, adrloop, source_subr=["length"])
- g.add_connection(adrloop, adrbase, sink_subr=["a"])
- g.add_connection(fi, adrbase, source_subr=["base"], sink_subr=["b"])
- g.add_connection(adrbase, adrbuffer)
- g.add_connection(adrbuffer, dma)
- g.add_connection(dma, cast)
- g.add_connection(cast, unpack)
- g.add_connection(unpack, vtg, sink_ep="pixels")
- g.add_connection(fi, vtg, sink_ep="timing", source_subr=[
- "hres", "hsync_start", "hsync_end", "hscan",
- "vres", "vsync_start", "vsync_end", "vscan"])
- g.add_connection(vtg, fifo)
- self._comp_actor = CompositeActor(g)
-
- self.bank = csrgen.Bank(fi.actor.get_registers(), address=address)
-
- # VGA clock input
- self.vga_clk = fifo.actor.vga_clk
-
- # Pads
- self.vga_psave_n = Signal()
- self.vga_hsync_n = fifo.actor.vga_hsync_n
- self.vga_vsync_n = fifo.actor.vga_vsync_n
- self.vga_sync_n = Signal()
- self.vga_blank_n = Signal()
- self.vga_r = fifo.actor.vga_r
- self.vga_g = fifo.actor.vga_g
- self.vga_b = fifo.actor.vga_b
+ for n, lasmim in enumerate(lasmims):
+ dma = spi.DMAReadController(dma_lasmi.Reader(lasmim), spi.MODE_EXTERNAL, length_reset=640*480*4)
+ cast = structuring.Cast(lasmim.dw, packed_pixels, reverse_to=True)
+ unpack = structuring.Unpack(pack_factor, pixel_layout)
+
+ g.add_connection(dma, cast)
+ g.add_connection(cast, unpack)
+ g.add_connection(unpack, self.blender, sink_subr=["i"+str(n)])
- def get_fragment(self):
- comb = [
- self.vga_sync_n.eq(0),
- self.vga_psave_n.eq(1),
- self.vga_blank_n.eq(1)
+ self.comb += dma.generator.trigger.eq(self._enable.storage)
+ setattr(self, "dma"+str(n), dma)
+
+ vtg = VTG()
+ fifo = FIFO()
+ g.add_connection(self.fi, vtg, sink_ep="timing")
+ g.add_connection(self.blender, vtg, sink_ep="pixels")
+ g.add_connection(vtg, fifo)
+ self.submodules += CompositeActor(g)
+
+ self.comb += [
+ pads.hsync_n.eq(fifo.vga_hsync_n),
+ pads.vsync_n.eq(fifo.vga_vsync_n),
+ pads.r.eq(fifo.vga_r),
+ pads.g.eq(fifo.vga_g),
+ pads.b.eq(fifo.vga_b),
+ pads.psave_n.eq(1)
]
- return self.bank.get_fragment() \
- + self._comp_actor.get_fragment() \
- + Fragment(comb)
projects / litex.git / blobdiff