-from migen.fhdl import structure as f
+from migen.fhdl.structure import *
from migen.bus import wishbone
-class Inst:
+class LM32:
def __init__(self):
- self.ibus = i = wishbone.Master("lm32i")
- self.dbus = d = wishbone.Master("lm32d")
- f.declare_signal(self, "interrupt", f.BV(32))
- f.declare_signal(self, "ext_break")
- self._inst = f.Instance("lm32_top",
- [("I_ADR_O", i.adr_o),
- ("I_DAT_O", i.dat_o),
- ("I_SEL_O", i.sel_o),
- ("I_CYC_O", i.cyc_o),
- ("I_STB_O", i.stb_o),
- ("I_WE_O", i.we_o),
- ("I_CTI_O", i.cti_o),
- ("I_LOCK_O", f.BV(1)),
- ("I_BTE_O", i.bte_o),
- ("D_ADR_O", d.adr_o),
- ("D_DAT_O", d.dat_o),
- ("D_SEL_O", d.sel_o),
- ("D_CYC_O", d.cyc_o),
- ("D_STB_O", d.stb_o),
- ("D_WE_O", d.we_o),
- ("D_CTI_O", d.cti_o),
- ("D_LOCK_O", f.BV(1)),
- ("D_BTE_O", d.bte_o)],
- [("interrupt", self.interrupt),
- #("ext_break", self.ext_break),
- ("I_DAT_I", i.dat_i),
- ("I_ACK_I", i.ack_i),
- ("I_ERR_I", i.err_i),
- ("I_RTY_I", f.BV(1)),
- ("D_DAT_I", d.dat_i),
- ("D_ACK_I", d.ack_i),
- ("D_ERR_I", d.err_i),
- ("D_RTY_I", f.BV(1))],
- [],
- "clk_i",
- "rst_i",
- "lm32")
+ self.ibus = i = wishbone.Interface()
+ self.dbus = d = wishbone.Interface()
+ self.interrupt = Signal(BV(32))
+ self.ext_break = Signal()
+ self._inst = Instance("lm32_top",
+ Instance.ClockPort("clk_i"),
+ Instance.ResetPort("rst_i"),
+
+ Instance.Input("interrupt", self.interrupt),
+ #Instance.Input("ext_break", self.ext_break),
+
+ Instance.Output("I_ADR_O", BV(32)),
+ Instance.Output("I_DAT_O", i.dat_w),
+ Instance.Output("I_SEL_O", i.sel),
+ Instance.Output("I_CYC_O", i.cyc),
+ Instance.Output("I_STB_O", i.stb),
+ Instance.Output("I_WE_O", i.we),
+ Instance.Output("I_CTI_O", i.cti),
+ Instance.Output("I_LOCK_O", BV(1)),
+ Instance.Output("I_BTE_O", i.bte),
+ Instance.Input("I_DAT_I", i.dat_r),
+ Instance.Input("I_ACK_I", i.ack),
+ Instance.Input("I_ERR_I", i.err),
+ Instance.Input("I_RTY_I", BV(1)),
+
+ Instance.Output("D_ADR_O", BV(32)),
+ Instance.Output("D_DAT_O", d.dat_w),
+ Instance.Output("D_SEL_O", d.sel),
+ Instance.Output("D_CYC_O", d.cyc),
+ Instance.Output("D_STB_O", d.stb),
+ Instance.Output("D_WE_O", d.we),
+ Instance.Output("D_CTI_O", d.cti),
+ Instance.Output("D_LOCK_O", BV(1)),
+ Instance.Output("D_BTE_O", d.bte),
+ Instance.Input("D_DAT_I", d.dat_r),
+ Instance.Input("D_ACK_I", d.ack),
+ Instance.Input("D_ERR_I", d.err),
+ Instance.Input("D_RTY_I", BV(1)))
def get_fragment(self):
comb = [
- f.Assign(self._inst.ins["I_RTY_I"], 0),
- f.Assign(self._inst.ins["D_RTY_I"], 0)
+ self._inst.get_io("I_RTY_I").eq(0),
+ self._inst.get_io("D_RTY_I").eq(0),
+ self.ibus.adr.eq(self._inst.get_io("I_ADR_O")[2:]),
+ self.dbus.adr.eq(self._inst.get_io("D_ADR_O")[2:])
]
- return f.Fragment(comb=comb, instances=[self._inst])
\ No newline at end of file
+ return Fragment(comb=comb, instances=[self._inst])