lite*: finish ModuleTransformer adaptations (need to be tested on board)

[litex.git] / misoclib / mem / litesata / core / link / __init__.py

diff --git a/misoclib/mem/litesata/core/link/__init__.py b/misoclib/mem/litesata/core/link/__init__.py
index 74e3d611be1d7ec3621ff632c44fc59577130b4c..4c96398ddda07d545d6bc6ae4e19c691515fb344 100644 (file)
--- a/misoclib/mem/litesata/core/link/__init__.py
+++ b/misoclib/mem/litesata/core/link/__init__.py
@@ -35,7 +35,7 @@ class LiteSATALinkTX(Module):
 
                # inserter CONT and scrambled data between
                # CONT and next primitive
-               cont = BufferizeEndpoints(LiteSATACONTInserter(phy_description(32)), "source")
+               cont = BufferizeEndpoints("source")(LiteSATACONTInserter(phy_description(32)))
                self.submodules += cont
 
                # datas / primitives mux
@@ -121,7 +121,7 @@ class LiteSATALinkRX(Module):
                self.submodules += fsm
 
                # CONT remover
-               cont = BufferizeEndpoints(LiteSATACONTRemover(phy_description(32)), "source")
+               cont = BufferizeEndpoints("source")(LiteSATACONTRemover(phy_description(32)))
                self.submodules += cont
                self.comb += Record.connect(phy.source, cont.sink)