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resolve internal (nmigen_soc) imports
[nmigen-soc.git]
/
nmigen_soc
/
wishbone
/
sram.py
diff --git
a/nmigen_soc/wishbone/sram.py
b/nmigen_soc/wishbone/sram.py
index f6734b2ef40c6407867d44df2caa8991619e1b05..ffb8f63da0c3a84cad1391deba5eeb363fdad8ef 100644
(file)
--- a/
nmigen_soc/wishbone/sram.py
+++ b/
nmigen_soc/wishbone/sram.py
@@
-1,7
+1,7
@@
from nmigen import Elaboratable, Memory, Module
from nmigen.utils import log2_int
-from .bus import Interface
+from
nmigen.wishbone
.bus import Interface
__all__ = ["SRAM"]