bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / av.mdwn

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 94937abb0f00782ce7fd2b349811048e97547fe2..797ba30ecf7645bcd34eda3be0258042c141bcd9 100644 (file)
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -2,69 +2,91 @@
 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
 <!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
 
-# DRAFT Fixed Point Signed Max
+# DRAFT Minimum/Maximum (Rc=1)
 
-X-Form
-
-* maxs  RT,RA,RB (Rc=0)
-* maxs. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    if   (RA) > (RB) then RT <- (RA)
-    else                  RT <- (RB)
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-
-# DRAFT Fixed Point Unsigned Max
-
-X-Form
-
-* maxu  RT,RA,RB (Rc=0)
-* maxu. RT,RA,RB (Rc=1)
+MM-Form
 
-Pseudo-code:
-
-    if   (RA) >u (RB) then RT <- (RA)
-    else                   RT <- (RB)
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-
-# DRAFT Fixed Point Signed Min
-
-X-Form
-
-* mins  RT,RA,RB (Rc=0)
-* mins. RT,RA,RB (Rc=1)
+* minmax. RT,RA,RB,MMM (Rc=1)
 
 Pseudo-code:
 
-    if   (RA) < (RB) then RT <- (RA)
-    else                  RT <- (RB)
+    a <- (RA|0)
+    b <- (RB)
+    if MMM[0] then  # word mode
+        # shift left by XLEN/2 to make the dword comparison
+        # do word comparison of the original inputs
+        a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
+        b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
+    if MMM[1] then  # signed mode
+        # invert sign bits to make the unsigned comparison
+        # do signed comparison of the original inputs
+        a[0] <- ¬a[0]
+        b[0] <- ¬b[0]
+    # if Rc = 1 then store the result of comparing a and b to CR0
+    if Rc = 1 then
+        if a <u b then
+            CR0 <- 0b100 || XER[SO]
+        if a = b then
+            CR0 <- 0b001 || XER[SO]
+        if a >u b then
+            CR0 <- 0b010 || XER[SO]
+    if MMM[2] then  # max mode
+        # swap a and b to make the less than comparison do
+        # greater than comparison of the original inputs
+        t <- a
+        a <- b
+        b <- t
+    # store the entire selected source (even in word mode)
+    # if Rc = 1 then store the result of comparing a and b to CR0
+    if a <u b then RT <- (RA|0)
+    else           RT <- (RB)
 
 Special Registers Altered:
 
     CR0                     (if Rc=1)
 
-# DRAFT Fixed Point Unsigned Min
+# DRAFT Minimum/Maximum
 
-X-Form
+MM-Form
 
-* minu  RT,RA,RB (Rc=0)
-* minu. RT,RA,RB (Rc=1)
+* minmax RT,RA,RB,MMM (Rc=0)
 
 Pseudo-code:
 
-    if   (RA) <u (RB) then RT <- (RA)
-    else                   RT <- (RB)
+    a <- (RA|0)
+    b <- (RB)
+    if MMM[0] then  # word mode
+        # shift left by XLEN/2 to make the dword comparison
+        # do word comparison of the original inputs
+        a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
+        b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
+    if MMM[1] then  # signed mode
+        # invert sign bits to make the unsigned comparison
+        # do signed comparison of the original inputs
+        a[0] <- ¬a[0]
+        b[0] <- ¬b[0]
+    # if Rc = 1 then store the result of comparing a and b to CR0
+    # if Rc = 1 then
+    #     if a <u b then
+    #         CR0 <- 0b100 || XER[SO]
+    #     if a = b then
+    #         CR0 <- 0b001 || XER[SO]
+    #     if a >u b then
+    #         CR0 <- 0b010 || XER[SO]
+    if MMM[2] then  # max mode
+        # swap a and b to make the less than comparison do
+        # greater than comparison of the original inputs
+        t <- a
+        a <- b
+        b <- t
+    # store the entire selected source (even in word mode)
+    # if Rc = 1 then store the result of comparing a and b to CR0
+    if a <u b then RT <- (RA|0)
+    else           RT <- (RB)
 
 Special Registers Altered:
 
-    CR0                     (if Rc=1)
+    None
 
 # DRAFT Average Add
 
@@ -157,15 +179,83 @@ Special Registers Altered:
 X-Form
 
 * cprop RT,RA,RB (Rc=0)
-* cprop RT,RA,RB (Rc=1)
+* cprop. RT,RA,RB (Rc=1)
 
 Pseudo-code:
 
     P <- (RA)
     G <- (RB)
     temp <- (P|G)+G
-    RT <- temp^P 
+    RT <- temp^P
 
 Special Registers Altered:
 
     CR0                    (if Rc=1)
+
+# DRAFT Bitmanip Masked
+
+BM2-Form
+
+* bmask  RT,RA,RB,bm,L
+
+Pseudo-code:
+
+    if _RB = 0 then mask <- [1] * XLEN
+    else mask <- (RB)
+    ra <- (RA) & mask
+    a1 <- ra
+    if bm[4] = 0 then a1 <- ¬ra
+    mode2 <- bm[2:3]
+    if mode2 = 0 then a2 <- (¬ra)+1
+    if mode2 = 1 then a2 <- ra-1
+    if mode2 = 2 then a2 <- ra+1
+    if mode2 = 3 then a2 <- ¬(ra+1)
+    a1 <- a1 & mask
+    a2 <- a2 & mask
+    # select operator
+    mode3 <- bm[0:1]
+    if mode3 = 0 then result <- a1 | a2
+    if mode3 = 1 then result <- a1 & a2
+    if mode3 = 2 then result <- a1 ^ a2
+    if mode3 = 3 then result <- undefined([0]*XLEN)
+    result <- result & mask
+    # optionally restore masked-out bits
+    if L = 1 then
+        result <- result | (RA & ¬mask)
+    RT <- result
+
+Special Registers Altered:
+
+    None
+
+# Load Floating-Point Immediate
+
+DX-Form
+
+* fmvis FRS,D
+
+Pseudo-code:
+
+    bf16 <- d0 || d1 || d2
+    fp32 <- bf16 || [0]*16
+    FRS  <- DOUBLE(fp32)
+
+Special Registers Altered:
+
+    None
+
+# Float Replace Lower-Half Single, Immediate
+
+DX-Form
+
+* fishmv FRS,D
+
+Pseudo-code:
+
+    fp32 <- SINGLE((FRS))
+    fp32[16:31] <- d0 || d1 || d2
+    FRS <- DOUBLE(fp32)
+
+Special Registers Altered:
+
+    None