P <- (RA)
G <- (RB)
temp <- (P|G)+G
- RT <- temp^P
+ RT <- temp^P
Special Registers Altered:
CR0 (if Rc=1)
+
+# DRAFT Bitmanip Masked
+
+BM2-Form
+
+* bmask RT,RA,RB,bm
+
+Pseudo-code:
+
+ if _RB = 0 then mask <- [1] * XLEN
+ else mask <- (RB)
+ ra <- (RA) & mask
+ a1 <- ra
+ if bm[4] = 0 then a1 <- ¬ra
+ mode2 <- bm[2:3]
+ if mode2 = 0 then a2 <- (¬ra)+1
+ if mode2 = 1 then a2 <- ra-1
+ if mode2 = 2 then a2 <- ra+1
+ if mode2 = 3 then a2 <- ¬(ra+1)
+ a1 <- a1 & mask
+ a2 <- a2 & mask
+ # select operator
+ mode3 <- bm[0:1]
+ if mode3 = 0 then result <- a1 | a2
+ if mode3 = 1 then result <- a1 & a2
+ if mode3 = 2 then result <- a1 ^ a2
+ if mode3 = 3 then result <- undefined([0]*XLEN)
+ result <- result & mask
+ # optionally restore masked-out bits
+ if L = 1 then
+ result <- result | (RA & ¬mask)
+ RT <- result
+
+Special Registers Altered:
+
+ None
+
+# Load Floating-Point Immediate
+
+DX-Form
+
+* fmvis FRS,D
+
+Pseudo-code:
+
+ bf16 <- d0 || d1 || d2
+ fp32 <- bf16 || [0]*16
+ FRS <- DOUBLE(fp32)
+
+Special Registers Altered:
+
+ None
+
+# Float Replace Lower-Half Single, Immediate
+
+DX-Form
+
+* fishmv FRS,D
+
+Pseudo-code:
+
+ fp32 <- SINGLE((FRS))
+ fp32[16:31] <- d0 || d1 || d2
+ FRS <- DOUBLE(fp32)
+
+Special Registers Altered:
+
+ None