bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / bitmanip.mdwn

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index 3f73b0b894583e8cfb2b871988c5b593f6412382..1f8081d7a2df09c165c982f668f52dc08f4fdec4 100644 (file)
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -1,95 +1,93 @@
-<!-- Draft Instructions here described in https://libre-soc.org/openpower/sv/bitmanip/ -->
+<!-- Draft Instructions here described in -->
+<!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
 <!-- These instructions are *not yet official* -->
 
-# Ternary Bitwise Logic Immediate
+# Gather instruction
 
-TLI-Form
+X-Form
 
-* ternlogi RT, RA, RB, TLI
+* gbbd RT,RA
 
 Pseudo-code:
 
-    result <- [0] * XLEN
-    do i = 0 to XLEN - 1
-      idx <- (RT)[i] || (RA)[i] || (RB)[i]
-      result[i] <- TLI[7-idx]
+    result <- [0] * 64
+    do j = 0 to 7
+        do k = 0 to 7
+            b <- (RA)[k*8+j]
+            result[j*8+k] <- b
     RT <- result
 
 Special Registers Altered:
 
-    None
+    CR0                    (if Rc=1)
 
-# Generalized Bit-Reverse
+# Ternary Bitwise Logic Immediate
 
-X-Form
+TLI-Form
 
-* grev RT, RA, RB (Rc=0)
-* grev. RT, RA, RB (Rc=1)
+* ternlogi RT,RA,RB,TLI (Rc=0)
+* ternlogi. RT,RA,RB,TLI (Rc=1)
 
 Pseudo-code:
 
     result <- [0] * XLEN
     do i = 0 to XLEN - 1
-      idx <- ((RB) ^ i) % XLEN
-      result[i] <- (RA)[idx]
+      idx <- (RT)[i] || (RA)[i] || (RB)[i]
+      result[i] <- TLI[7-idx]
     RT <- result
 
 Special Registers Altered:
 
     CR0                    (if Rc=1)
 
-# Generalized Bit-Reverse Immediate
+# Add With Shift By Immediate
 
-XB-Form
+Z23-Form
 
-* grevi RT, RA, XBI (Rc=0)
-* grevi. RT, RA, XBI (Rc=1)
+* sadd RT,RA,RB,SH (Rc=0)
+* sadd. RT,RA,RB,SH (Rc=1)
 
 Pseudo-code:
 
-    result <- [0] * XLEN
-    do i = 0 to XLEN - 1
-      idx <- (XBI ^ i) % XLEN
-      result[i] <- (RA)[idx]
-    RT <- result
+    n <- (RB)
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 
 Special Registers Altered:
 
     CR0                    (if Rc=1)
 
-# Generalized Bit-Reverse Word
+# Add With Shift By Immediate Word
 
-X-Form
+Z23-Form
 
-* grevw RT, RA, RB (Rc=0)
-* grevw. RT, RA, RB (Rc=1)
+* saddw RT,RA,RB,SH (Rc=0)
+* saddw. RT,RA,RB,SH (Rc=1)
 
 Pseudo-code:
 
-    result <- [0] * XLEN # MSB half just stays zeroed
-    do i = 0 to XLEN / 2 - 1
-      idx <- ((RB) ^ i) % (XLEN / 2)
-      result[i] <- (RA)[idx]
-    RT <- result
+    n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
+    if (RB)[XLEN/2] = 1 then
+        n[0:XLEN/2-1] <- [1]*(XLEN/2)
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 
 Special Registers Altered:
 
     CR0                    (if Rc=1)
 
-# Generalized Bit-Reverse Word Immediate
+# Add With Shift By Immediate Unsigned Word
 
-X-Form
+Z23-Form
 
-* grevwi RT, RA, SH (Rc=0)
-* grevwi. RT, RA, SH (Rc=1)
+* sadduw RT,RA,RB,SH (Rc=0)
+* sadduw. RT,RA,RB,SH (Rc=1)
 
 Pseudo-code:
 
-    result <- [0] * XLEN # MSB half just stays zeroed
-    do i = 0 to XLEN / 2 - 1
-      idx <- (SH ^ i) % (XLEN / 2)
-      result[i] <- (RA)[idx]
-    RT <- result
+    n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 
 Special Registers Altered: