<!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
<!-- These instructions are *not yet official* -->
-# Ternary Bitwise Logic Immediate
-
-TLI-Form
-
-* ternlogi RT,RA,RB,TLI
-* ternlogi. RT,RA,RB,TLI
-
-Pseudo-code:
-
- result <- [0] * XLEN
- do i = 0 to XLEN - 1
- idx <- (RT)[i] || (RA)[i] || (RB)[i]
- result[i] <- TLI[7-idx]
- RT <- result
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Generalized Bit-Reverse
+# Gather instruction
X-Form
-* grev RT,RA,RB (Rc=0)
-* grev. RT,RA,RB (Rc=1)
+* gbbd RT,RA
Pseudo-code:
- result <- [0] * XLEN
- b <- EXTZ64(RB)
- do i = 0 to XLEN - 1
- idx <- b[64-log2(XLEN):63] ^ i
- result[i] <- (RA)[idx]
+ result <- [0] * 64
+ do j = 0 to 7
+ do k = 0 to 7
+ b <- (RA)[k*8+j]
+ result[j*8+k] <- b
RT <- result
Special Registers Altered:
CR0 (if Rc=1)
-# Generalized Bit-Reverse Immediate
+# Ternary Bitwise Logic Immediate
-XB-Form
+TLI-Form
-* grevi RT,RA,XBI (Rc=0)
-* grevi. RT,RA,XBI (Rc=1)
+* ternlogi RT,RA,RB,TLI (Rc=0)
+* ternlogi. RT,RA,RB,TLI (Rc=1)
Pseudo-code:
result <- [0] * XLEN
do i = 0 to XLEN - 1
- idx <- XBI[6-log2(XLEN):5] ^ i
- result[i] <- (RA)[idx]
+ idx <- (RT)[i] || (RA)[i] || (RB)[i]
+ result[i] <- TLI[7-idx]
RT <- result
Special Registers Altered:
CR0 (if Rc=1)
-# Generalized Bit-Reverse Word
-
-X-Form
-
-* grevw RT,RA,RB (Rc=0)
-* grevw. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
- result <- [0] * (XLEN / 2)
- a <- (RA)[XLEN/2:XLEN-1]
- b <- EXTZ64(RB)
- do i = 0 to XLEN / 2 - 1
- idx <- b[64-log2(XLEN/2):63] ^ i
- result[i] <- a[idx]
- RT <- ([0] * (XLEN / 2)) || result
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Generalized Bit-Reverse Word Immediate
+# Add With Shift By Immediate
-X-Form
+Z23-Form
-* grevwi RT,RA,SH (Rc=0)
-* grevwi. RT,RA,SH (Rc=1)
+* sadd RT,RA,RB,SH (Rc=0)
+* sadd. RT,RA,RB,SH (Rc=1)
Pseudo-code:
- result <- [0] * (XLEN / 2)
- a <- (RA)[XLEN/2:XLEN-1]
- do i = 0 to XLEN / 2 - 1
- idx <- SH[5-log2(XLEN/2):4] ^ i
- result[i] <- a[idx]
- RT <- ([0] * (XLEN / 2)) || result
+ n <- (RB)
+ m <- ((0b0 || SH) + 1)
+ RT <- (n[m:XLEN-1] || [0]*m) + (RA)
Special Registers Altered:
CR0 (if Rc=1)
-# Add With Shift By Immediate
+# Add With Shift By Immediate Word
Z23-Form
-* shadd RT,RA,RB,sm (Rc=0)
-* shadd. RT,RA,RB,sm (Rc=1)
+* saddw RT,RA,RB,SH (Rc=0)
+* saddw. RT,RA,RB,SH (Rc=1)
Pseudo-code:
- n <- (RB)
- m <- ((0b0 || sm) + 1)
+ n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
+ if (RB)[XLEN/2] = 1 then
+ n[0:XLEN/2-1] <- [1]*(XLEN/2)
+ m <- ((0b0 || SH) + 1)
RT <- (n[m:XLEN-1] || [0]*m) + (RA)
Special Registers Altered:
CR0 (if Rc=1)
-# Add With Shift By Immediate Unsinged Word
+# Add With Shift By Immediate Unsigned Word
Z23-Form
-* shadduw RT,RA,RB,sm (Rc=0)
-* shadduw. RT,RA,RB,sm (Rc=1)
+* sadduw RT,RA,RB,SH (Rc=0)
+* sadduw. RT,RA,RB,SH (Rc=1)
Pseudo-code:
n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
- m <- ((0b0 || sm) + 1)
+ m <- ((0b0 || SH) + 1)
RT <- (n[m:XLEN-1] || [0]*m) + (RA)
Special Registers Altered: