bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / bitmanip.mdwn

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index f428bd1b762d978eb552cb78932d0e44514e1a8b..1f8081d7a2df09c165c982f668f52dc08f4fdec4 100644 (file)
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -1,11 +1,32 @@
-<!-- Draft Instructions here described in https://libre-soc.org/openpower/sv/bitmanip/ -->
+<!-- Draft Instructions here described in -->
+<!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
 <!-- These instructions are *not yet official* -->
 
+# Gather instruction
+
+X-Form
+
+* gbbd RT,RA
+
+Pseudo-code:
+
+    result <- [0] * 64
+    do j = 0 to 7
+        do k = 0 to 7
+            b <- (RA)[k*8+j]
+            result[j*8+k] <- b
+    RT <- result
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
 # Ternary Bitwise Logic Immediate
 
 TLI-Form
 
-* ternlogi RT, RA, RB, TLI
+* ternlogi RT,RA,RB,TLI (Rc=0)
+* ternlogi. RT,RA,RB,TLI (Rc=1)
 
 Pseudo-code:
 
@@ -17,4 +38,57 @@ Pseudo-code:
 
 Special Registers Altered:
 
-    None
+    CR0                    (if Rc=1)
+
+# Add With Shift By Immediate
+
+Z23-Form
+
+* sadd RT,RA,RB,SH (Rc=0)
+* sadd. RT,RA,RB,SH (Rc=1)
+
+Pseudo-code:
+
+    n <- (RB)
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
+# Add With Shift By Immediate Word
+
+Z23-Form
+
+* saddw RT,RA,RB,SH (Rc=0)
+* saddw. RT,RA,RB,SH (Rc=1)
+
+Pseudo-code:
+
+    n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
+    if (RB)[XLEN/2] = 1 then
+        n[0:XLEN/2-1] <- [1]*(XLEN/2)
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
+# Add With Shift By Immediate Unsigned Word
+
+Z23-Form
+
+* sadduw RT,RA,RB,SH (Rc=0)
+* sadduw. RT,RA,RB,SH (Rc=1)
+
+Pseudo-code:
+
+    n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)