added english language description for lbzsx instruction

[openpower-isa.git] / openpower / isa / bitmanip.mdwn

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index 89515ec977385f3ffd7f91b253f795c7d55d69c8..3b0cc8e8da302a7e7a21b0ed69b329e914be8327 100644 (file)
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -6,8 +6,8 @@
 
 TLI-Form
 
-* ternlogi RT,RA,RB,TLI
-* ternlogi. RT,RA,RB,TLI
+* ternlogi RT,RA,RB,TLI (Rc=0)
+* ternlogi. RT,RA,RB,TLI (Rc=1)
 
 Pseudo-code:
 
@@ -21,123 +21,54 @@ Special Registers Altered:
 
     CR0                    (if Rc=1)
 
-# Generalized Bit-Reverse
-
-X-Form
-
-* grev RT,RA,RB (Rc=0)
-* grev. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    result <- [0] * XLEN
-    b <- EXTZ64(RB)
-    do i = 0 to XLEN - 1
-      idx <- b[64-log2(XLEN):63] ^ i
-      result[i] <- (RA)[idx]
-    RT <- result
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Generalized Bit-Reverse Immediate
-
-XB-Form
-
-* grevi RT,RA,XBI (Rc=0)
-* grevi. RT,RA,XBI (Rc=1)
-
-Pseudo-code:
-
-    result <- [0] * XLEN
-    do i = 0 to XLEN - 1
-      idx <- XBI[6-log2(XLEN):5] ^ i
-      result[i] <- (RA)[idx]
-    RT <- result
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Generalized Bit-Reverse Word
-
-X-Form
-
-* grevw RT,RA,RB (Rc=0)
-* grevw. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    result <- [0] * (XLEN / 2)
-    a <- (RA)[XLEN/2:XLEN-1]
-    b <- EXTZ64(RB)
-    do i = 0 to XLEN / 2 - 1
-      idx <- b[64-log2(XLEN/2):63] ^ i
-      result[i] <- a[idx]
-    RT <- ([0] * (XLEN / 2)) || result
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Generalized Bit-Reverse Word Immediate
+# Add With Shift By Immediate
 
-X-Form
+Z23-Form
 
-* grevwi RT,RA,SH (Rc=0)
-* grevwi. RT,RA,SH (Rc=1)
+* sadd RT,RA,RB,SH (Rc=0)
+* sadd. RT,RA,RB,SH (Rc=1)
 
 Pseudo-code:
 
-    result <- [0] * (XLEN / 2)
-    a <- (RA)[XLEN/2:XLEN-1]
-    do i = 0 to XLEN / 2 - 1
-      idx <- SH[5-log2(XLEN/2):4] ^ i
-      result[i] <- a[idx]
-    RT <- ([0] * (XLEN / 2)) || result
+    n <- (RB)
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 
 Special Registers Altered:
 
     CR0                    (if Rc=1)
 
-# Add With Shift By Immediate
+# Add With Shift By Immediate Word
 
 Z23-Form
 
-* shadd RT,RA,RB,sm (Rc=0)
-* shadd. RT,RA,RB,sm (Rc=1)
+* saddw RT,RA,RB,SH (Rc=0)
+* saddw. RT,RA,RB,SH (Rc=1)
 
 Pseudo-code:
 
-    n <- (RB)
-    switch (sm)
-        case (0): sum[0:XLEN-1] = (n[0:XLEN-1-1] || [0]*1) + (RA)
-        case (1): sum[0:XLEN-1] = (n[0:XLEN-2-1] || [0]*2) + (RA)
-        case (2): sum[0:XLEN-1] = (n[0:XLEN-3-1] || [0]*3) + (RA)
-        default:  sum[0:XLEN-1] = (n[0:XLEN-4-1] || [0]*4) + (RA)
-    RT <- sum
+    n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
+    if (RB)[XLEN/2] = 1 then
+        n[0:XLEN/2-1] <- [1]*(XLEN/2)
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 
 Special Registers Altered:
 
     CR0                    (if Rc=1)
 
-# Add With Shift By Immediate Unsinged Word
+# Add With Shift By Immediate Unsigned Word
 
 Z23-Form
 
-* shadduw RT,RA,RB,sm (Rc=0)
-* shadduw. RT,RA,RB,sm (Rc=1)
+* sadduw RT,RA,RB,SH (Rc=0)
+* sadduw. RT,RA,RB,SH (Rc=1)
 
 Pseudo-code:
 
     n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
-    switch (sm)
-        case (0): sum[0:XLEN-1] = (n[0:XLEN-1-1] || [0]*1) + (RA)
-        case (1): sum[0:XLEN-1] = (n[0:XLEN-2-1] || [0]*2) + (RA)
-        case (2): sum[0:XLEN-1] = (n[0:XLEN-3-1] || [0]*3) + (RA)
-        default:  sum[0:XLEN-1] = (n[0:XLEN-4-1] || [0]*4) + (RA)
-    RT <- sum
+    m <- ((0b0 || SH) + 1)
+    RT <- (n[m:XLEN-1] || [0]*m) + (RA)
 
 Special Registers Altered: