Added spaces and brackets for lbzux instruction

[openpower-isa.git] / openpower / isa / fixedload.mdwn

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 20252b28088b80d39b6ae712ec8d031b149b96aa..5e704587bf9b8c5be88d46f744c03eabe182df9a 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -78,13 +78,13 @@ Pseudo-code:
 
 Description:
 
-Let the effective address (EA) be the sum (RA)+ D. The
-byte in storage addressed by EA is loaded into RT[56:63].
-RT[0:55] are set to 0.
+    Let the effective address (EA) be the sum (RA)+ D. The
+    byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
 
-EA is placed into register RA.
+    EA is placed into register RA.
 
-If RA=0 or RA=RT, the instruction form is invalid.
+    If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered:
 
@@ -102,11 +102,15 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
-Description:Let the effective address (EA) be the sum (RA)+ (RB).
-The byte in storage addressed by EA is loaded into
-RT56:63. RT0:55 are set to 0.
-EA is placed into register RA.
-If RA=0 or RA=RT, the instruction form is invalid.
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    The byte in storage addressed by EA is loaded into
+    RT[56:63]. RT[0:55] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered: