Added spaces and brackets for lhzu instruction

[openpower-isa.git] / openpower / isa / fixedload.mdwn

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index e9b4da88b46f856c37faaec157ed67d15e7e3cfd..94d59dd0bea6ef563115f509405a873e6ce5fc4b 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -160,11 +160,15 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
-Description:Let the effective address (EA) be the sum (RA)+ D. The
-halfword in storage addressed by EA is loaded into
-RT48:63. RT 0:47 are set to 0.
-EA is placed into register RA.
-If RA=0 or RA=RT, the instruction form is invalid.
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D. The
+    halfword in storage addressed by EA is loaded into
+    RT[48:63]. RT[0:47] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered: