b <- (RA|0)
EA <- b + EXTS(D)
- RT <- [0]*56 || MEM(EA, 1)
+ RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
Special Registers Altered:
b <- (RA|0)
EA <- b + (RB)
- RT <- [0] * 56 || MEM(EA, 1)
+ RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
Special Registers Altered:
Pseudo-code:
EA <- (RA) + EXTS(D)
- RT <- [0] * 56 || MEM(EA, 1)
+ RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
RA <- EA
Special Registers Altered:
Pseudo-code:
EA <- (RA) + (RB)
- RT <- [0] * 56 || MEM(EA, 1)
+ RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
RA <- EA
Special Registers Altered:
b <- (RA|0)
EA <- b + EXTS(D)
- RT <- [0] * 48 || MEM(EA, 2)
+ RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
Special Registers Altered:
b <- (RA|0)
EA <- b + (RB)
- RT <- [0] * 48 || MEM(EA, 2)
+ RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
Special Registers Altered:
Pseudo-code:
EA <- (RA) + EXTS(D)
- RT <- [0] * 48 || MEM(EA, 2)
+ RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
RA <- EA
Special Registers Altered:
Pseudo-code:
EA <- (RA) + (RB)
- RT <- [0] * 48 || MEM(EA, 2)
+ RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
RA <- EA
Special Registers Altered:
None
-<!-- MISSING stq -->
-
<!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
# Load Halfword Byte-Reverse Indexed
None
-<!-- MISSING sthbrx -->
-
# Load Word Byte-Reverse Indexed
X-Form
None
-<!-- MISSING stwbrx -->
-
<!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
None
-<!-- MISSING stdbrx -->
-
<!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
# Load Multiple Word
b <- (RA|0)
EA <- b + EXTS(D)
- r <- RT
+ r <- RT[0:63]
do while r <= 31
GPR(r) <- [0]*32 || MEM(EA, 4)
r <- r + 1
None
-<!-- MISSING stmw -->
-
-