bug 1236: add extra argument to svstep: RA.

[openpower-isa.git] / openpower / isa / fixedload.mdwn

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 607a247a1492a3844fd2defebbcac2a9e1494323..a6c7f9883280619734fd3b938f13d9d576a2fcd3 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -36,7 +36,14 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + EXTS(D)
-    RT <- [0]*56 || MEM(EA, 1)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ D.
+
+    The byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
 
 Special Registers Altered:
 
@@ -54,6 +61,13 @@ Pseudo-code:
     EA <- b + (RB)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+    The byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
+
 Special Registers Altered:
 
     None
@@ -70,6 +84,17 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+
+    The byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -86,6 +111,17 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    The byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -102,6 +138,13 @@ Pseudo-code:
     EA <- b + EXTS(D)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ D.
+
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are set to 0.
+
 Special Registers Altered:
 
     None
@@ -118,6 +161,13 @@ Pseudo-code:
     EA <- b + (RB)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are set to 0.
+
 Special Registers Altered:
 
     None
@@ -134,6 +184,17 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -150,6 +211,17 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -166,6 +238,13 @@ Pseudo-code:
     EA <- b + EXTS(D)
     RT <- EXTS(MEM(EA, 2))
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ D.
+
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
 Special Registers Altered:
 
     None
@@ -182,6 +261,13 @@ Pseudo-code:
     EA <- b + (RB)
     RT <- EXTS(MEM(EA, 2))
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
 Special Registers Altered:
 
     None
@@ -198,6 +284,16 @@ Pseudo-code:
     RT <- EXTS(MEM(EA, 2))
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -214,6 +310,17 @@ Pseudo-code:
     RT <- EXTS(MEM(EA, 2))
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -230,6 +337,13 @@ Pseudo-code:
     EA <- b + EXTS(D)
     RT <- [0] * 32 || MEM(EA, 4)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ D.
+
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are set to 0.
+
 Special Registers Altered:
 
     None
@@ -246,6 +360,13 @@ Pseudo-code:
     EA <- b + (RB)
     RT <- [0] * 32 || MEM(EA, 4)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are set to 0.
+
 Special Registers Altered:
 
     None
@@ -262,6 +383,17 @@ Pseudo-code:
     RT <- [0]*32 || MEM(EA, 4)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -278,6 +410,17 @@ Pseudo-code:
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -294,6 +437,13 @@ Pseudo-code:
     EA <- b + EXTS(DS || 0b00)
     RT <- EXTS(MEM(EA, 4))
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ (DS||0b00).
+
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are filled with a copy of bit 0 of the loaded word.
+
 Special Registers Altered:
 
     None
@@ -310,6 +460,13 @@ Pseudo-code:
     EA <- b + (RB)
     RT <- EXTS(MEM(EA, 4))
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are filled with a copy of bit 0 of the loaded word.
+
 Special Registers Altered:
 
     None
@@ -326,6 +483,17 @@ Pseudo-code:
     RT <- EXTS(MEM(EA, 4))
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are filled with a copy of bit 0 of the loaded word.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -342,6 +510,12 @@ Pseudo-code:
     EA <- b + EXTS(DS || 0b00)
     RT <- MEM(EA, 8)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ (DS||0b00).
+
+    The doubleword in storage addressed by EA is loaded into RT.
+
 Special Registers Altered:
 
     None
@@ -358,6 +532,12 @@ Pseudo-code:
     EA <- b + (RB)
     RT <- MEM(EA, 8)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+    The doubleword in storage addressed by EA is loaded into RT.
+
 Special Registers Altered:
 
     None
@@ -374,6 +554,16 @@ Pseudo-code:
     RT <- MEM(EA, 8)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (DS||0b00).
+
+    The doubleword in storage addressed by EA is loaded into RT.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -390,6 +580,16 @@ Pseudo-code:
     RT <- MEM(EA, 8)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    The doubleword in storage addressed by EA is loaded into RT.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -431,6 +631,27 @@ Pseudo-code:
     EA <- b + EXTS(DQ || 0b0000)
     RTp <- MEM(EA, 16)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ (DQ||0b0000).
+    The quadword in storage addressed by EA is loaded into register pair RTp.
+
+    If RTp is odd or RTp=RA, the instruction form is invalid.
+    If RTp=RA, an attempt to execute this instruction will
+    invoke the system illegal instruction error handler. (The
+    RTp=RA case includes the case of RTp=RA=0.)
+
+    The quadword in storage addressed by EA is loaded
+    into an even-odd pair of GPRs as follows. In
+    Big-Endian mode, the even-numbered GPR is loaded
+    with the doubleword from storage addressed by EA
+    and the odd-numbered GPR is loaded with the double-
+    word addressed by EA+8. In Little-Endian mode, the
+    even-numbered GPR is loaded with the byte-reversed
+    doubleword from storage addressed by EA+8 and the
+    odd-numbered GPR is loaded with the byte-reversed
+    doubleword addressed by EA.
+
 Special Registers Altered:
 
     None
@@ -450,6 +671,15 @@ Pseudo-code:
     load_data <- MEM(EA, 2)
     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+(RB).
+
+    Bits 0:7 of the halfword in storage addressed by EA are
+    loaded into RT[56:63]. Bits 8:15 of the halfword in storage
+    addressed by EA are loaded into RT[48:55].
+    RT[0:47] are set to 0.
+
 Special Registers Altered:
 
     None
@@ -468,6 +698,18 @@ Pseudo-code:
     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
                     || load_data[8:15]  || load_data[0:7])
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+    Bits 0:7 of the word in storage addressed
+    by EA are loaded into RT[56:63]. Bits 8:15 of the word in
+    storage addressed by EA are loaded into RT[48:55]. Bits
+    16:23 of the word in storage addressed by EA are
+    loaded into RT[40:47]. Bits 24:31 of the word in storage
+    addressed by EA are loaded into RT 32:39.
+    RT[0:31] are set to 0.
+
 Special Registers Altered:
 
     None
@@ -491,6 +733,23 @@ Pseudo-code:
         || load_data[24:31] || load_data[16:23]
         || load_data[8:15]  || load_data[0:7])
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+(RB).
+
+    Bits 0:7 of the doubleword in storage addressed by EA
+    are loaded into RT[56:63]. Bits 8:15 of the doubleword in
+    storage addressed by EA are loaded into RT[48:55]. Bits
+    16:23 of the doubleword in storage addressed by EA
+    are loaded into RT[40:47]. Bits 24:31 of the doubleword in
+    storage addressed by EA are loaded into RT 32:39. Bits
+    32:39 of the doubleword in storage addressed by EA
+    are loaded into RT[24:31]. Bits 40:47 of the doubleword in
+    storage addressed by EA are loaded into RT[16:23]. Bits
+    48:55 of the doubleword in storage addressed by EA
+    are loaded into RT[8:15]. Bits 56:63 of the doubleword in
+    storage addressed by EA are loaded into RT[0:7].
+
 Special Registers Altered:
 
     None
@@ -499,7 +758,7 @@ Special Registers Altered:
 
 # Load Multiple Word
 
-DQ-Form
+D-Form
 
 * lmw RT,D(RA)
 
@@ -513,6 +772,22 @@ Pseudo-code:
         r <- r + 1
         EA <- EA + 4
 
+Description:
+
+    Let n = (32-RT). Let the effective address (EA) be the
+    sum (RA|0)+ D.
+
+    n consecutive words starting at EA are loaded into the
+    low-order 32 bits of GPRs RT through 31. The
+    high-order 32 bits of these GPRs are set to zero.
+
+    If RA is in the range of registers to be loaded, including
+    the case in which RA=0, the instruction form is invalid.
+
+    This instruction is not supported in Little-Endian mode.
+    If it is executed in Little-Endian mode, the system align-
+    ment error handler is invoked.
+
 Special Registers Altered:
 
     None