Description:
Let the effective address (EA) be the sum (RA|0)+ D.
- The byte in storage addressed by EA is loaded into
- RT[56:63]. RT[0:55] are set to 0.
+
+ The byte in storage addressed by EA is loaded into RT[56:63].
+ RT[0:55] are set to 0.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum
- (RA|0)+ (RB). The byte in storage addressed by EA is
- loaded into RT[56:63] . RT[0:55] are set to 0.
+ Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+ The byte in storage addressed by EA is loaded into RT[56:63].
+ RT[0:55] are set to 0.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum (RA)+ D. The
- byte in storage addressed by EA is loaded into RT[56:63].
+ Let the effective address (EA) be the sum (RA)+ D.
+
+ The byte in storage addressed by EA is loaded into RT[56:63].
RT[0:55] are set to 0.
EA is placed into register RA.
Description:
Let the effective address (EA) be the sum (RA)+ (RB).
- The byte in storage addressed by EA is loaded into
- RT[56:63]. RT[0:55] are set to 0.
+
+ The byte in storage addressed by EA is loaded into RT[56:63].
+ RT[0:55] are set to 0.
EA is placed into register RA.
Description:
Let the effective address (EA) be the sum (RA|0)+ D.
- The halfword in storage addressed by EA is loaded into
- RT[48:63]. RT[0:47] are set to 0.
+
+ The halfword in storage addressed by EA is loaded into RT[48:63].
+ RT[0:47] are set to 0.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum
- (RA|0)+ (RB). The halfword in storage addressed by
- EA is loaded into RT 48:63. RT 0:47 are set to 0.
+ Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+ The halfword in storage addressed by EA is loaded into RT[48:63].
+ RT[0:47] are set to 0.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum (RA)+ D. The
- halfword in storage addressed by EA is loaded into
- RT[48:63]. RT[0:47] are set to 0.
+ Let the effective address (EA) be the sum (RA)+ D.
+
+ The halfword in storage addressed by EA is loaded into RT[48:63].
+ RT[0:47] are set to 0.
EA is placed into register RA.
Description:
Let the effective address (EA) be the sum (RA)+ (RB).
- The halfword in storage addressed by EA is loaded into
- RT[48:63]. RT[0:47] are set to 0.
+
+ The halfword in storage addressed by EA is loaded into RT[48:63].
+ RT[0:47] are set to 0.
EA is placed into register RA.
Description:
Let the effective address (EA) be the sum (RA|0)+ D.
- The halfword in storage addressed by EA is loaded into
- RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
- loaded halfword.
+
+ The halfword in storage addressed by EA is loaded into RT[48:63].
+ RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum
- (RA|0)+ (RB). The halfword in storage addressed by
- EA is loaded into RT[48:63] . RT[0:47] are filled with a copy
- of bit 0 of the loaded halfword.
+ Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+ The halfword in storage addressed by EA is loaded into RT[48:63].
+ RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum (RA)+ D. The
- halfword in storage addressed by EA is loaded into
- RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
- loaded halfword.
+ Let the effective address (EA) be the sum (RA)+ D.
+ The halfword in storage addressed by EA is loaded into RT[48:63].
+ RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
EA is placed into register RA.
Description:
Let the effective address (EA) be the sum (RA)+ (RB).
- The halfword in storage addressed by EA is loaded into
- RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
- loaded halfword.
+
+ The halfword in storage addressed by EA is loaded into RT[48:63].
+ RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
EA is placed into register RA.
RT <- [0] * 32 || MEM(EA, 4)
Description:
+
Let the effective address (EA) be the sum (RA|0)+ D.
- The word in storage addressed by EA is loaded into
- RT[32:63]. RT[0:31] are set to 0.
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are set to 0.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum
- (RA|0)+ (RB). The word in storage addressed by EA is
- loaded into RT[32:63] . RT[0:31] are set to 0.
+ Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are set to 0.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum (RA)+ D. The
- word in storage addressed by EA is loaded into
- RT[32:63]. RT[0:31] are set to 0.
+ Let the effective address (EA) be the sum (RA)+ D.
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are set to 0.
EA is placed into register RA.
Description:
Let the effective address (EA) be the sum (RA)+ (RB).
- The word in storage addressed by EA is loaded into
- RT[32:63]. RT[0:31] are set to 0.
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are set to 0.
EA is placed into register RA.
Description:
- Let the effective address (EA) be the sum
- (RA|0)+ (DS||0b00). The word in storage addressed by
- EA is loaded into RT[32:63] . RT[0:31] are filled with a copy
- of bit 0 of the loaded word.
+ Let the effective address (EA) be the sum (RA|0)+ (DS||0b00).
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are filled with a copy of bit 0 of the loaded word.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum
- (RA|0)+ (RB). The word in storage addressed by EA is
- loaded into RT 32:63 . RT 0:31 are filled with a copy of bit 0
- of the loaded word.
+ Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are filled with a copy of bit 0 of the loaded word.
Special Registers Altered:
Description:
Let the effective address (EA) be the sum (RA)+ (RB).
- The word in storage addressed by EA is loaded into
- RT[32:63]. RT[0:31] are filled with a copy of bit 0 of the
- loaded word.
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are filled with a copy of bit 0 of the loaded word.
EA is placed into register RA.
Description:
- Let the effective address (EA) be the sum
- (RA|0)+ (DS||0b00). The doubleword in storage
- addressed by EA is loaded into RT.
+ Let the effective address (EA) be the sum (RA|0)+ (DS||0b00).
+
+ The doubleword in storage addressed by EA is loaded into RT.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum
- (RA|0)+ (RB). The doubleword in storage addressed by
- EA is loaded into RT.
+ Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+ The doubleword in storage addressed by EA is loaded into RT.
Special Registers Altered:
Description:
- Let the effective address (EA) be the sum
- (RA)+ (DS||0b00). The doubleword in storage
- addressed by EA is loaded into RT.
+ Let the effective address (EA) be the sum (RA)+ (DS||0b00).
+
+ The doubleword in storage addressed by EA is loaded into RT.
EA is placed into register RA.
Description:
Let the effective address (EA) be the sum (RA)+ (RB).
- The doubleword in storage addressed by EA is loaded
- into RT.
+
+ The doubleword in storage addressed by EA is loaded into RT.
EA is placed into register RA.
EA <- b + EXTS(DQ || 0b0000)
RTp <- MEM(EA, 16)
-Description
+Description:
- Let the effective address (EA) be the sum (RA|0)+
- (DQ||0b0000). The quadword in storage addressed by
- EA is loaded into register pair RTp.
+ Let the effective address (EA) be the sum (RA|0)+ (DQ||0b0000).
+ The quadword in storage addressed by EA is loaded into register pair RTp.
If RTp is odd or RTp=RA, the instruction form is invalid.
If RTp=RA, an attempt to execute this instruction will
load_data <- MEM(EA, 2)
RT <- [0]*48 || load_data[8:15] || load_data[0:7]
+Description:
+
+ Let the effective address (EA) be the sum (RA|0)+(RB).
+
+ Bits 0:7 of the halfword in storage addressed by EA are
+ loaded into RT[56:63]. Bits 8:15 of the halfword in storage
+ addressed by EA are loaded into RT[48:55].
+ RT[0:47] are set to 0.
+
Special Registers Altered:
None
RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
|| load_data[8:15] || load_data[0:7])
+Description:
+
+ Let the effective address (EA) be the sum (RA|0)+ (RB).
+
+ Bits 0:7 of the word in storage addressed
+ by EA are loaded into RT[56:63]. Bits 8:15 of the word in
+ storage addressed by EA are loaded into RT[48:55]. Bits
+ 16:23 of the word in storage addressed by EA are
+ loaded into RT[40:47]. Bits 24:31 of the word in storage
+ addressed by EA are loaded into RT 32:39.
+ RT[0:31] are set to 0.
+
Special Registers Altered:
None
|| load_data[24:31] || load_data[16:23]
|| load_data[8:15] || load_data[0:7])
+Description:
+
+ Let the effective address (EA) be the sum (RA|0)+(RB).
+
+ Bits 0:7 of the doubleword in storage addressed by EA
+ are loaded into RT[56:63]. Bits 8:15 of the doubleword in
+ storage addressed by EA are loaded into RT[48:55]. Bits
+ 16:23 of the doubleword in storage addressed by EA
+ are loaded into RT[40:47]. Bits 24:31 of the doubleword in
+ storage addressed by EA are loaded into RT 32:39. Bits
+ 32:39 of the doubleword in storage addressed by EA
+ are loaded into RT[24:31]. Bits 40:47 of the doubleword in
+ storage addressed by EA are loaded into RT[16:23]. Bits
+ 48:55 of the doubleword in storage addressed by EA
+ are loaded into RT[8:15]. Bits 56:63 of the doubleword in
+ storage addressed by EA are loaded into RT[0:7].
+
Special Registers Altered:
None
# Load Multiple Word
-DQ-Form
+D-Form
* lmw RT,D(RA)
r <- r + 1
EA <- EA + 4
+Description:
+
+ Let n = (32-RT). Let the effective address (EA) be the
+ sum (RA|0)+ D.
+
+ n consecutive words starting at EA are loaded into the
+ low-order 32 bits of GPRs RT through 31. The
+ high-order 32 bits of these GPRs are set to zero.
+
+ If RA is in the range of registers to be loaded, including
+ the case in which RA=0, the instruction form is invalid.
+
+ This instruction is not supported in Little-Endian mode.
+ If it is executed in Little-Endian mode, the system align-
+ ment error handler is invoked.
+
Special Registers Altered:
None