bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / fixedload.mdwn

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index e4cc4fa87f211249f29715b46e217464aa15f450..a6c7f9883280619734fd3b938f13d9d576a2fcd3 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -631,7 +631,7 @@ Pseudo-code:
     EA <- b + EXTS(DQ || 0b0000)
     RTp <- MEM(EA, 16)
 
-Description
+Description:
 
     Let the effective address (EA) be the sum (RA|0)+ (DQ||0b0000).
     The quadword in storage addressed by EA is loaded into register pair RTp.
@@ -676,7 +676,7 @@ Description:
     Let the effective address (EA) be the sum (RA|0)+(RB).
 
     Bits 0:7 of the halfword in storage addressed by EA are
-    loaded into RT 56:63. Bits 8:15 of the halfword in storage
+    loaded into RT[56:63]. Bits 8:15 of the halfword in storage
     addressed by EA are loaded into RT[48:55].
     RT[0:47] are set to 0.