added english language description for lbzsx instruction

[openpower-isa.git] / openpower / isa / fixedloadshift.mdwn

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index b401e12c76d9d82bc921405bb9a6765f6dd5c07b..481547c9bcb626f0877d9ae57ea029e00c1826b6 100644 (file)
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -26,18 +26,26 @@
 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
 
 
-# Load Byte and Zero Shifted Indexed 
+# Load Byte and Zero Shifted Indexed
 
 X-Form
 
-* lbzsx RT,RA,RB,sm
+* lbzsx RT,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB) << (sm+1)
+    EA <- b + (RB) << (SH+1)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 
+Description:
+
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and (RA|0).
+    The byte in storage addressed by EA is loaded into
+    RT[56:63]. RT[0:55] are set to 0.
+
+
 Special Registers Altered:
 
     None
@@ -46,11 +54,11 @@ Special Registers Altered:
 
 X-Form
 
-* lbzsux RT,RA,RB,sm
+* lbzsux RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB) << (sm+1)
+    EA <- (RA) + (RB) << (SH+1)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
@@ -62,12 +70,12 @@ Special Registers Altered:
 
 X-Form
 
-* lhzsx RT,RA,RB,sm
+* lhzsx RT,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB) << (sm+1)
+    EA <- b + (RB) << (SH+1)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 
 Special Registers Altered:
@@ -78,11 +86,11 @@ Special Registers Altered:
 
 X-Form
 
-* lhzsux RT,RA,RB,sm
+* lhzsux RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB) << (sm+1)
+    EA <- (RA) + (RB) << (SH+1)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
@@ -90,31 +98,31 @@ Special Registers Altered:
 
     None
 
-# Load Halfword Algebraic Indexed
+# Load Halfword Algebraic Shifted Indexed
 
 X-Form
 
-* lhax RT,RA,RB
+* lhasx RT,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) << (SH+1)
     RT <- EXTS(MEM(EA, 2))
 
 Special Registers Altered:
 
     None
 
-# Load Halfword Algebraic with Update Indexed
+# Load Halfword Algebraic Shifted with Update Indexed
 
 X-Form
 
-* lhaux RT,RA,RB
+* lhasux RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB) << (SH+1)
     RT <- EXTS(MEM(EA, 2))
     RA <- EA
 
@@ -122,31 +130,31 @@ Special Registers Altered:
 
     None
 
-# Load Word and Zero Indexed
+# Load Word and Zero Shifted Indexed
 
 X-Form
 
-* lwzx RT,RA,RB
+* lwzsx RT,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) << (SH+1)
     RT <- [0] * 32 || MEM(EA, 4)
 
 Special Registers Altered:
 
     None
 
-# Load Word and Zero with Update Indexed
+# Load Word and Zero Shifted with Update Indexed
 
 X-Form
 
-* lwzux RT,RA,RB
+* lwzsux RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB) << (SH+1)
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- EA
 
@@ -154,31 +162,31 @@ Special Registers Altered:
 
     None
 
-# Load Word Algebraic Indexed
+# Load Word Algebraic Shifted Indexed
 
 X-Form
 
-* lwax RT,RA,RB
+* lwasx RT,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) << (SH+1)
     RT <- EXTS(MEM(EA, 4))
 
 Special Registers Altered:
 
     None
 
-# Load Word Algebraic with Update Indexed
+# Load Word Algebraic Shifted with Update Indexed
 
 X-Form
 
-* lwaux RT,RA,RB
+* lwasux RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB) << (SH+1)
     RT <- EXTS(MEM(EA, 4))
     RA <- EA
 
@@ -186,31 +194,31 @@ Special Registers Altered:
 
     None
 
-# Load Doubleword Indexed
+# Load Doubleword Shifted Indexed
 
 X-Form
 
-* ldx RT,RA,RB
+* ldsx RT,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) << (SH+1)
     RT <- MEM(EA, 8)
 
 Special Registers Altered:
 
     None
 
-# Load Doubleword with Update Indexed
+# Load Doubleword Shifted with Update Indexed
 
 X-Form
 
-* ldux RT,RA,RB
+* ldsux RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB) << (SH+1)
     RT <- MEM(EA, 8)
     RA <- EA
 
@@ -220,16 +228,16 @@ Special Registers Altered:
 
 <!-- byte-reverse shifted -->
 
-# Load Halfword Byte-Reverse Indexed
+# Load Halfword Byte-Reverse Shifted Indexed
 
 X-Form
 
-* lhbrx RT,RA,RB
+* lhbrsx RT,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) << (SH+1)
     load_data <- MEM(EA, 2)
     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 
@@ -237,16 +245,16 @@ Special Registers Altered:
 
     None
 
-# Load Word Byte-Reverse Indexed
+# Load Word Byte-Reverse Shifted Indexed
 
 X-Form
 
-* lwbrx RT,RA,RB
+* lwbrsx RT,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) << (SH+1)
     load_data <- MEM(EA, 4)
     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
                     || load_data[8:15]  || load_data[0:7])
@@ -258,16 +266,16 @@ Special Registers Altered:
 
 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 
-# Load Doubleword Byte-Reverse Indexed
+# Load Doubleword Byte-Reverse Shifted Indexed
 
 X-Form
 
-* ldbrx RT,RA,RB
+* ldbrsx RT,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) << (SH+1)
     load_data <- MEM(EA, 8)
     RT <- (load_data[56:63] || load_data[48:55]
         || load_data[40:47] || load_data[32:39]