Description:
Let the effective address (EA) be the sum of the contents of
- register RB shifted by (SH+1), and (RA).
+ register RB shifted by (SH+1), and the contents of register RA.
- The byte in storage addressed by EA is
- loaded into RT[56:63] . RT[0:55] are set to 0.
+ The byte in storage addressed by EA is loaded into RT[56:63].
+ RT[0:55] are set to 0.
EA is placed into register RA.
Let the effective address (EA) be the sum of the contents of
register RB shifted by (SH+1), and (RA|0).
- The halfword in storage addressed by EA is loaded into
- RT[48:63]. RT[0:47] are set to 0.
+ The halfword in storage addressed by EA is loaded into RT[48:63].
+ RT[0:47] are set to 0.
Special Registers Altered:
Description:
Let the effective address (EA) be the sum of the contents of
- register RB shifted by (SH+1), and (RA).
+ register RB shifted by (SH+1), and the contents of register RA.
The halfword in storage addressed by EA is loaded into RT[48:63].
RT[0:47] are set to 0.
RT <- EXTS(MEM(EA, 2))
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum of the contents of
+ register RB shifted by (SH+1), and the contents of register RA.
+
+ The halfword in storage addressed by EA is loaded into RT[48:63].
+ RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+ EA is placed into register RA.
+
+ If RA=0 or RA=RT, the instruction form is invalid.
+
Special Registers Altered:
None
EA <- b + (RB) << (SH+1)
RT <- [0] * 32 || MEM(EA, 4)
+Description:
+
+ Let the effective address (EA) be the sum of the contents of
+ register RB shifted by (SH+1), and (RA|0).
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are set to 0.
+
Special Registers Altered:
None
RT <- [0] * 32 || MEM(EA, 4)
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum of the contents of
+ register RB shifted by (SH+1), and the contents of register RA.
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are set to 0.
+
+ EA is placed into register RA.
+
+ If RA=0 or RA=RT, the instruction form is invalid.
+
Special Registers Altered:
None
EA <- b + (RB) << (SH+1)
RT <- EXTS(MEM(EA, 4))
+Description:
+
+ Let the effective address (EA) be the sum of the contents of
+ register RB shifted by (SH+1), and (RA|0).
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are filled with a copy of bit 0 of the loaded word.
+
Special Registers Altered:
None
RT <- EXTS(MEM(EA, 4))
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum of the contents of
+ register RB shifted by (SH+1), and the contents of register RA.
+
+ The word in storage addressed by EA is loaded into RT[32:63].
+ RT[0:31] are filled with a copy of bit 0 of the loaded word.
+
+ EA is placed into register RA.
+
+ If RA=0 or RA=RT, the instruction form is invalid.
+
Special Registers Altered:
None
EA <- b + (RB) << (SH+1)
RT <- MEM(EA, 8)
+Description:
+
+ Let the effective address (EA) be the sum of the contents of
+ register RB shifted by (SH+1), and (RA|0).
+
+ The doubleword in storage addressed by EA is loaded into RT.
+
Special Registers Altered:
None
RT <- MEM(EA, 8)
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum of the contents of
+ register RB shifted by (SH+1), and (RA).
+
+ The doubleword in storage addressed by EA is loaded into RT.
+
+ EA is placed into register RA.
+
+ If RA=0 or RA=RT, the instruction form is invalid.
+
Special Registers Altered:
None
load_data <- MEM(EA, 2)
RT <- [0]*48 || load_data[8:15] || load_data[0:7]
+Description:
+
+ Let the effective address (EA) be the sum of the contents of
+ register RB shifted by (SH+1), and (RA|0).
+
+ Bits 0:7 of the halfword in storage addressed by EA are
+ loaded into RT[56:63]. Bits 8:15 of the halfword in storage
+ addressed by EA are loaded into RT[48:55].
+ RT[0:47] are set to 0.
+
+
Special Registers Altered:
None
RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
|| load_data[8:15] || load_data[0:7])
+Description:
+
+ Let the effective address (EA) be the sum of the contents of
+ register RB shifted by (SH+1), and (RA|0).
+
+ Bits 0:7 of the word in storage addressed
+ by EA are loaded into RT[56:63]. Bits 8:15 of the word in
+ storage addressed by EA are loaded into RT[48:55]. Bits
+ 16:23 of the word in storage addressed by EA are
+ loaded into RT[40:47]. Bits 24:31 of the word in storage
+ addressed by EA are loaded into RT 32:39.
+ RT[0:31] are set to 0.
+
Special Registers Altered:
None
|| load_data[24:31] || load_data[16:23]
|| load_data[8:15] || load_data[0:7])
+Description:
+
+ Let the effective address (EA) be the sum of the contents of
+ register RB shifted by (SH+1), and (RA|0).
+
+ Bits 0:7 of the doubleword in storage addressed by EA
+ are loaded into RT[56:63]. Bits 8:15 of the doubleword in
+ storage addressed by EA are loaded into RT[48:55]. Bits
+ 16:23 of the doubleword in storage addressed by EA
+ are loaded into RT[40:47]. Bits 24:31 of the doubleword in
+ storage addressed by EA are loaded into RT 32:39. Bits
+ 32:39 of the doubleword in storage addressed by EA
+ are loaded into RT[24:31]. Bits 40:47 of the doubleword in
+ storage addressed by EA are loaded into RT[16:23]. Bits
+ 48:55 of the doubleword in storage addressed by EA
+ are loaded into RT[8:15]. Bits 56:63 of the doubleword in
+ storage addressed by EA are loaded into RT[0:7].
+
+
Special Registers Altered:
None