added english language description for lbzsx instruction

[openpower-isa.git] / openpower / isa / fixedlogical.mdwn

diff --git a/openpower/isa/fixedlogical.mdwn b/openpower/isa/fixedlogical.mdwn
index 43aafe515edaf0aa249ff711da6013d47e987598..01eeffb1defc5255faea6b16c52a26e2c3a23bd4 100644 (file)
--- a/openpower/isa/fixedlogical.mdwn
+++ b/openpower/isa/fixedlogical.mdwn
@@ -512,4 +512,72 @@ Special Registers Altered:
 
     None
 
-<!-- Checked March 2021 -->
+# Centrifuge Doubleword
+
+X-Form
+
+* cfuged RA,RS,RB
+
+Pseudo-code:
+
+    ptr0 <- 0
+    ptr1 <- 0
+    result[0:63] <- 0
+    do i = 0 to 63
+        if (RB)[i] = 0 then
+            result[ptr0] <- (RS)[i]
+            ptr0 <- ptr0 + 1
+        if (RB)[63-i] = 1 then
+            result[63-ptr1] <- (RS)[63-i]
+            ptr1 <- ptr1 + 1
+    RA <- result
+
+Special Registers Altered:
+
+    None
+
+# Parallel Bits Extract Doubleword
+
+X-Form
+
+* pextd RA,RS,RB
+
+Pseudo-code:
+
+    result[0:63] <- 0
+    mask <- (RB)
+    m <- 0
+    k <- 0
+    do while m < 64
+        if (RB)[63-m] = 1 then
+            result[63-k] <- (RS)[63-m]
+            k <- k + 1
+        m <- m + 1
+    RA <- result
+
+Special Registers Altered:
+
+    None
+
+# Parallel Bits Deposit Doubleword
+
+X-Form
+
+* pdepd RA,RS,RB
+
+Pseudo-code:
+
+    result[0:63] <- 0
+    mask <- (RB)
+    m <- 0
+    k <- 0
+    do while m < 64
+        if (RB)[63-m] = 1 then
+            result[63-m] <- (RS)[63-k]
+            k <- k + 1
+        m <- m + 1
+    RA <- result
+
+Special Registers Altered:
+
+    None