added english language description for lbzsx instruction

[openpower-isa.git] / openpower / isa / fixedlogical.mdwn

diff --git a/openpower/isa/fixedlogical.mdwn b/openpower/isa/fixedlogical.mdwn
index b1332fe8cb5de07d1e01e27796d1c55a20997abd..01eeffb1defc5255faea6b16c52a26e2c3a23bd4 100644 (file)
--- a/openpower/isa/fixedlogical.mdwn
+++ b/openpower/isa/fixedlogical.mdwn
@@ -18,7 +18,7 @@ D-Form
 
 Pseudo-code:
 
-    RA <- (RS) & XLCASTU(UI)
+    RA <- (RS) & EXTZ(UI)
 
 Special Registers Altered:
 
@@ -32,7 +32,7 @@ D-Form
 
 Pseudo-code:
 
-    RA <- (RS) | XLCASTU(UI)
+    RA <- (RS) | EXTZ(UI)
 
 Special Registers Altered:
 
@@ -46,7 +46,7 @@ D-Form
 
 Pseudo-code:
 
-    RA <- (RS) & XLCASTU(UI || [0]*16)
+    RA <- (RS) & EXTZ(UI || [0]*16)
 
 Special Registers Altered:
 
@@ -60,7 +60,7 @@ D-Form
 
 Pseudo-code:
 
-    RA <- (RS) | XLCASTU(UI || [0]*16)
+    RA <- (RS) | EXTZ(UI || [0]*16)
 
 Special Registers Altered:
 
@@ -74,7 +74,7 @@ D-Form
 
 Pseudo-code:
 
-    RA <- (RS) ^ XLCASTU(UI || [0]*16)
+    RA <- (RS) ^ EXTZ(UI || [0]*16)
 
 Special Registers Altered:
 
@@ -88,7 +88,7 @@ D-Form
 
 Pseudo-code:
 
-    RA <- (RS) ^ XLCASTU(UI)
+    RA <- (RS) ^ EXTZ(UI)
 
 Special Registers Altered:
 
@@ -223,7 +223,7 @@ X-Form
 
 Pseudo-code:
 
-    RA <- EXTSXL(RS, 8)
+    RA <- EXTSXL(RS, XLEN/8)
 
 Special Registers Altered:
 
@@ -238,7 +238,7 @@ X-Form
 
 Pseudo-code:
 
-    RA <- EXTSXL(RS, 16)
+    RA <- EXTSXL(RS, XLEN/4)
 
 Special Registers Altered:
 
@@ -274,11 +274,11 @@ X-Form
 Pseudo-code:
 
     n <- 0
-    do while n < 32
-       if (RS)[63-n] = 0b1 then
+    do while n < XLEN/2
+       if (RS)[XLEN-1-n] = 0b1 then
             leave
        n  <- n + 1
-    RA <- EXTZ64(n)
+    RA <- EXTZ(n)
 
 Special Registers Altered:
 
@@ -306,7 +306,7 @@ Special Registers Altered:
 
 X-Form
 
-* popcntb RA, RS
+* popcntb RA,RS
 
 Pseudo-code:
 
@@ -325,7 +325,7 @@ Special Registers Altered:
 
 X-Form
 
-* popcntw RA, RS
+* popcntw RA,RS
 
 Pseudo-code:
 
@@ -389,7 +389,7 @@ X-Form
 
 Pseudo-code:
 
-    RA <- EXTSXL(RS, 32)
+    RA <- EXTSXL(RS, XLEN/2)
 
 Special Registers Altered:
 
@@ -399,7 +399,7 @@ Special Registers Altered:
 
 X-Form
 
-* popcntd RA, RS
+* popcntd RA,RS
 
 Pseudo-code:
 
@@ -447,31 +447,137 @@ Pseudo-code:
        if (RS)[XLEN-1-n] = 0b1 then
             leave
        n  <- n + 1
-    RA <- EXTZ64(n)
+    RA <- EXTZ(n)
 
 Special Registers Altered:
 
     CR0                    (if Rc=1)
 
+# Count Leading Zeros Doubleword under bit Mask
+
+X-Form
+
+* cntlzdm RA,RS,RB
+
+Pseudo-code:
+
+    count <- 0
+    do i = 0 to 63
+        if (RB)[i] = 1 then
+            if (RS)[i] = 1 then leave
+            count <- count + 1
+    RA <- EXTZ64(count)
+
+Special Registers Altered:
+
+    None
+
+# Count Trailing Zeros Doubleword under bit Mask
+
+X-Form
+
+* cnttzdm RA,RS,RB
+
+Pseudo-code:
+
+    count <- 0
+    do i = 0 to 63
+        if (RB)[63-i] = 1 then
+            if (RS)[63-i] = 1 then leave
+            count <- count + 1
+    RA <- EXTZ64(count)
+
+Special Registers Altered:
+
+    None
+
 # Bit Permute Doubleword
 
 X-Form
 
-* bpermd RA,RS,RB]
+* bpermd RA,RS,RB
 
 Pseudo-code:
 
-    perm <- [0] * 8
+    perm <- [0] * (XLEN/8)
     for i = 0 to ((XLEN/8)-1)
        index <- (RS)[8*i:8*i+7]
        if index <u XLEN then
             perm[i] <- (RB)[index]
        else
             perm[i] <- 0
-    RA <- [0]*(XLEN-8) || perm[0:7]
+    RA <- [0]*(XLEN*7/8) || perm
 
 Special Registers Altered:
 
     None
 
-<!-- Checked March 2021 -->
+# Centrifuge Doubleword
+
+X-Form
+
+* cfuged RA,RS,RB
+
+Pseudo-code:
+
+    ptr0 <- 0
+    ptr1 <- 0
+    result[0:63] <- 0
+    do i = 0 to 63
+        if (RB)[i] = 0 then
+            result[ptr0] <- (RS)[i]
+            ptr0 <- ptr0 + 1
+        if (RB)[63-i] = 1 then
+            result[63-ptr1] <- (RS)[63-i]
+            ptr1 <- ptr1 + 1
+    RA <- result
+
+Special Registers Altered:
+
+    None
+
+# Parallel Bits Extract Doubleword
+
+X-Form
+
+* pextd RA,RS,RB
+
+Pseudo-code:
+
+    result[0:63] <- 0
+    mask <- (RB)
+    m <- 0
+    k <- 0
+    do while m < 64
+        if (RB)[63-m] = 1 then
+            result[63-k] <- (RS)[63-m]
+            k <- k + 1
+        m <- m + 1
+    RA <- result
+
+Special Registers Altered:
+
+    None
+
+# Parallel Bits Deposit Doubleword
+
+X-Form
+
+* pdepd RA,RS,RB
+
+Pseudo-code:
+
+    result[0:63] <- 0
+    mask <- (RB)
+    m <- 0
+    k <- 0
+    do while m < 64
+        if (RB)[63-m] = 1 then
+            result[63-m] <- (RS)[63-k]
+            k <- k + 1
+        m <- m + 1
+    RA <- result
+
+Special Registers Altered:
+
+    None