bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / fixedshift.mdwn

diff --git a/openpower/isa/fixedshift.mdwn b/openpower/isa/fixedshift.mdwn
index 96d781b1192504ba180af13efed6e388edb971f3..db59a6fa85bb2fea7f1892ab5af44678db6ca031 100644 (file)
--- a/openpower/isa/fixedshift.mdwn
+++ b/openpower/isa/fixedshift.mdwn
@@ -38,7 +38,7 @@ M-Form
 Pseudo-code:
 
     n <- (RB)[XLEN-5:XLEN-1]
-    r <- ROTL32((RS)[32:63], n)
+    r <- ROTL32((RS)[XLEN/2:XLEN-1], n)
     m <- MASK32(MB, ME)
     RA <- r & m
 
@@ -68,8 +68,8 @@ Special Registers Altered:
 
 MD-Form
 
-* rldicl RA,RS,SH,MB (Rc=0)
-* rldicl.  RA,RS,SH,MB (Rc=1)
+* rldicl RA,RS,sh,mb (Rc=0)
+* rldicl.  RA,RS,sh,mb (Rc=1)
 
 Pseudo-code:
 
@@ -87,8 +87,8 @@ Special Registers Altered:
 
 MD-Form
 
-* rldicr RA,RS,SH,ME (Rc=0)
-* rldicr.  RA,RS,SH,ME (Rc=1)
+* rldicr RA,RS,sh,me (Rc=0)
+* rldicr.  RA,RS,sh,me (Rc=1)
 
 Pseudo-code:
 
@@ -106,8 +106,8 @@ Special Registers Altered:
 
 MD-Form
 
-* rldic RA,RS,SH,MB (Rc=0)
-* rldic.  RA,RS,SH,MB (Rc=1)
+* rldic RA,RS,sh,mb (Rc=0)
+* rldic.  RA,RS,sh,mb (Rc=1)
 
 Pseudo-code:
 
@@ -125,8 +125,8 @@ Special Registers Altered:
 
 MDS-Form
 
-* rldcl RA,RS,RB,MB (Rc=0)
-* rldcl.  RA,RS,RB,MB (Rc=1)
+* rldcl RA,RS,RB,mb (Rc=0)
+* rldcl.  RA,RS,RB,mb (Rc=1)
 
 Pseudo-code:
 
@@ -144,8 +144,8 @@ Special Registers Altered:
 
 MDS-Form
 
-* rldcr RA,RS,RB,ME (Rc=0)
-* rldcr.  RA,RS,RB,ME (Rc=1)
+* rldcr RA,RS,RB,me (Rc=0)
+* rldcr.  RA,RS,RB,me (Rc=1)
 
 Pseudo-code:
 
@@ -163,8 +163,8 @@ Special Registers Altered:
 
 MD-Form
 
-* rldimi RA,RS,SH,MB (Rc=0)
-* rldimi.  RA,RS,SH,MB (Rc=1)
+* rldimi RA,RS,sh,mb (Rc=0)
+* rldimi.  RA,RS,sh,mb (Rc=1)
 
 Pseudo-code:
 
@@ -313,8 +313,8 @@ Special Registers Altered:
 
 XS-Form
 
-* sradi RA,RS,SH (Rc=0)
-* sradi.  RA,RS,SH (Rc=1)
+* sradi RA,RS,sh (Rc=0)
+* sradi.  RA,RS,sh (Rc=1)
 
 Pseudo-code:
 
@@ -341,13 +341,13 @@ X-Form
 
 Pseudo-code:
 
-    n <- (RB)[58:63]
-    r <- ROTL64((RS), 64-n)
-    if (RB)[57] = 0 then
-        m <-  MASK(n, 63)
-    else m <- [0]*64
+    n <- (RB)[XLEN-6:XLEN-1]
+    r <- ROTL64((RS), XLEN-n)
+    if (RB)[XLEN-7] = 0 then
+        m <-  MASK(n, (XLEN-1))
+    else m <- [0]*XLEN
     s <- (RS)[0]
-    RA <- r&m | ([s]*64)& ¬m
+    RA <- r&m | ([s]*XLEN)& ¬m
     carry <-  s & ((r&¬m) != 0)
     CA    <-  carry
     CA32  <-  carry
@@ -361,8 +361,8 @@ Special Registers Altered:
 
 XS-Form
 
-* extswsli RA,RS,SH (Rc=0)
-* extswsli.  RA,RS,SH (Rc=1)
+* extswsli RA,RS,sh (Rc=0)
+* extswsli.  RA,RS,sh (Rc=1)
 
 Pseudo-code: