If RA=0, the instruction form is invalid.
- Special Registers Altered:
+Special Registers Altered:
None
If RA=0, the instruction form is invalid.
- Special Registers Altered:
+Special Registers Altered:
None
If RA=0, the instruction form is invalid.
- Special Registers Altered:
+Special Registers Altered:
None
If RA=0, the instruction form is invalid.
- Special Registers Altered:
+Special Registers Altered:
None
If RA=0, the instruction form is invalid.
- Special Registers Altered:
+Special Registers Altered:
None
If RA=0, the instruction form is invalid.
- Special Registers Altered:
+Special Registers Altered:
None
MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
||(RS)[32:39])
+Description:
+
+ Let the effective address (EA) be the sum
+ (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
+ word in storage addressed by EA. (RS) [48:55] are stored
+ into bits 8:15 of the word in storage addressed by EA.
+ (RS)[40:47] are stored into bits 16:23 of the word in stor-
+ age addressed by EA. (RS) [32:39] are stored into bits
+ 24:31 of the word in storage addressed by EA.
+
Special Registers Altered:
None
|| (RS)[24:31] || (RS)[16:23]
|| (RS)[8:15] || (RS)[0:7])
+Description:
+
+ Let the effective address (EA) be the sum
+ (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
+ doubleword in storage addressed by EA. (RS) [48:55] are
+ stored into bits 8:15 of the doubleword in storage
+ addressed by EA. (RS) [40:47] are stored into bits 16:23 of
+ the doubleword in storage addressed by EA. (RS) [32:39]
+ are stored into bits 23:31 of the doubleword in storage
+ addressed by EA. (RS) [24:31] are stored into bits 32:39 of
+ the doubleword in storage addressed by EA. (RS) [16:23]
+ are stored into bits 40:47 of the doubleword in storage
+ addressed by EA. (RS)[8:15] are stored into bits 48:55 of
+ the doubleword in storage addressed by EA. (RS) [0:7]
+ are stored into bits 56:63 of the doubleword in storage
+ addressed by EA.
+
Special Registers Altered:
None
r <- r + 1
EA <- EA + 4
+Description:
+
+ Let n = (32-RS). Let the effective address (EA) be the
+ sum (RA|0)+ D.
+
+ n consecutive words starting at EA are stored from the
+ low-order 32 bits of GPRs RS through 31.
+
+ This instruction is not supported in Little-Endian mode.
+ If it is executed in Little-Endian mode, the system align-
+ ment error handler is invoked.
+
Special Registers Altered:
None