bug 1236: add extra argument to svstep: RA.

[openpower-isa.git] / openpower / isa / fixedstore.mdwn

diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
index 452b0bfec8e75c46392f24fe061f00f24e2bed9f..94c419e35e23b1fb0ad0e39b4b3ee08d0b7bf66a 100644 (file)
--- a/openpower/isa/fixedstore.mdwn
+++ b/openpower/isa/fixedstore.mdwn
@@ -80,7 +80,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -106,7 +106,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -176,7 +176,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -202,7 +202,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -272,7 +272,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -298,7 +298,7 @@ Description:
 
     If RA=0, the instruction form is invalid.
 
-    Special Registers Altered:
+Special Registers Altered:
 
     None
 
@@ -559,6 +559,18 @@ Pseudo-code:
         r <-  r + 1
         EA <-  EA + 4
 
+Description:
+
+    Let n = (32-RS). Let the effective address (EA) be the
+    sum (RA|0)+ D.
+
+    n consecutive words starting at EA are stored from the
+    low-order 32 bits of GPRs RS through 31.
+
+    This instruction is not supported in Little-Endian mode.
+    If it is executed in Little-Endian mode, the system align-
+    ment error handler is invoked.
+
 Special Registers Altered:
 
     None