Description:
-Let the effective address (EA) be the sum (RA|0)+ D.
-RS[56:63] are stored into the byte in storage addressed
-by EA.
+ Let the effective address (EA) be the sum (RA|0)+ D.
+ RS[56:63] are stored into the byte in storage addressed
+ by EA.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum
-(RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
-age addressed by EA.
+ Let the effective address (EA) be the sum
+ (RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
+ age addressed by EA.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum (RA)+ D.
-RS[56:63] are stored into the byte in storage addressed
-by EA.
+ Let the effective address (EA) be the sum (RA)+ D.
+ RS[56:63] are stored into the byte in storage addressed
+ by EA.
-EA is placed into register RA.
+ EA is placed into register RA.
-If RA=0, the instruction form is invalid.
+ If RA=0, the instruction form is invalid.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum (RA)+ (RB).
-RS[56:63] are stored into the byte in storage addressed
-by EA.
+ Let the effective address (EA) be the sum (RA)+ (RB).
+ RS[56:63] are stored into the byte in storage addressed
+ by EA.
-EA is placed into register RA.
+ EA is placed into register RA.
-If RA=0, the instruction form is invalid.
+ If RA=0, the instruction form is invalid.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum (RA|0)+ D.
-RS[48:63] are stored into the halfword in storage
-addressed by EA.
+ Let the effective address (EA) be the sum (RA|0)+ D.
+ RS[48:63] are stored into the halfword in storage
+ addressed by EA.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum
-(RA|0)+ (RB). RS[48:63] are stored into the halfword in
-storage addressed by EA.
+ Let the effective address (EA) be the sum
+ (RA|0)+ (RB). RS[48:63] are stored into the halfword in
+ storage addressed by EA.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum (RA)+ D.
-RS[48:63] are stored into the halfword in storage
-addressed by EA.
+ Let the effective address (EA) be the sum (RA)+ D.
+ RS[48:63] are stored into the halfword in storage
+ addressed by EA.
-EA is placed into register RA.
+ EA is placed into register RA.
-If RA=0, the instruction form is invalid.
+ If RA=0, the instruction form is invalid.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum (RA)+ (RB).
-RS[48:63] are stored into the halfword in storage
-addressed by EA.
+ Let the effective address (EA) be the sum (RA)+ (RB).
+ RS[48:63] are stored into the halfword in storage
+ addressed by EA.
-EA is placed into register RA.
+ EA is placed into register RA.
-If RA=0, the instruction form is invalid.
+ If RA=0, the instruction form is invalid.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum (RA|0)+ D.
-RS[32:63] are stored into the word in storage addressed
-by EA.
+ Let the effective address (EA) be the sum (RA|0)+ D.
+ RS[32:63] are stored into the word in storage addressed
+ by EA.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum
-(RA|0)+ (RB). RS[32:63] are stored into the word in stor-
-age addressed by EA.
+ Let the effective address (EA) be the sum
+ (RA|0)+ (RB). RS[32:63] are stored into the word in stor-
+ age addressed by EA.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum (RA)+ D.
-RS[32:63] are stored into the word in storage addressed
-by EA.
+ Let the effective address (EA) be the sum (RA)+ D.
+ RS[32:63] are stored into the word in storage addressed
+ by EA.
-EA is placed into register RA.
+ EA is placed into register RA.
-If RA=0, the instruction form is invalid.
+ If RA=0, the instruction form is invalid.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum (RA)+ (RB).
-RS[32:63] are stored into the word in storage addressed
-by EA.
+ Let the effective address (EA) be the sum (RA)+ (RB).
+ RS[32:63] are stored into the word in storage addressed
+ by EA.
-EA is placed into register RA.
+ EA is placed into register RA.
-If RA=0, the instruction form is invalid.
+ If RA=0, the instruction form is invalid.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum
-(RA|0)+ (DS||0b00). (RS) is stored into the doubleword
-in storage addressed by EA.
+ Let the effective address (EA) be the sum
+ (RA|0)+ (DS||0b00). (RS) is stored into the doubleword
+ in storage addressed by EA.
Special Registers Altered:
Description:
-Let the effective address (EA) be the sum
-(RA|0)+ (RB). (RS) is stored into the doubleword in
-storage addressed by EA.
+ Let the effective address (EA) be the sum
+ (RA|0)+ (RB). (RS) is stored into the doubleword in
+ storage addressed by EA.
Special Registers Altered:
MEM(EA, 8) <- (RS)
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum
+ (RA)+ (DS||0b00). (RS) is stored into the doubleword in
+ storage addressed by EA.
+
+ EA is placed into register RA.
+
+ If RA=0, the instruction form is invalid.
+
Special Registers Altered:
None
MEM(EA, 8) <- (RS)
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum (RA)+ (RB).
+ (RS) is stored into the doubleword in storage
+ addressed by EA.
+
+ EA is placed into register RA.
+
+ If RA=0, the instruction form is invalid.
+
Special Registers Altered:
None
EA <- b + EXTS(DS || 0b00)
MEM(EA, 16) <- RSp
+Description:
+
+ Let the effective address (EA) be the sum (RA|0)+
+ (DS||0b00). The contents of register pair RSp are
+ stored into the quadword in storage addressed by EA.
+
+ If RSp is odd, the instruction form is invalid.
+
+ The contents of an even-odd pair of GPRs is stored into
+ the quadword in storage addressed by EA as follows.
+ In Big-Endian mode, the even-numbered GPR is stored
+ into the doubleword in storage addressed by EA and
+ the odd-numbered GPR is stored into the doubleword
+ addressed by EA+8. In Little-Endian mode, the
+ even-numbered GPR is stored byte-reversed into the
+ doubleword in storage addressed by EA+8 and the
+ odd-numbered GPR is stored byte-reversed into the
+ doubleword addressed by EA.
+
Special Registers Altered:
None
EA <- b + (RB)
MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
+Description:
+
+ Let the effective address (EA) be the sum
+ (RA|0)+ (RB). (RS)56:63 are stored into bits 0:7 of the
+ halfword in storage addressed by EA. (RS) 48:55 are
+ stored into bits 8:15 of the halfword in storage
+ addressed by EA.
+
Special Registers Altered:
None
MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
||(RS)[32:39])
+Description:
+
+ Let the effective address (EA) be the sum
+ (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
+ word in storage addressed by EA. (RS) [48:55] are stored
+ into bits 8:15 of the word in storage addressed by EA.
+ (RS)[40:47] are stored into bits 16:23 of the word in stor-
+ age addressed by EA. (RS) [32:39] are stored into bits
+ 24:31 of the word in storage addressed by EA.
+
Special Registers Altered:
None
|| (RS)[24:31] || (RS)[16:23]
|| (RS)[8:15] || (RS)[0:7])
+Description:
+
+ Let the effective address (EA) be the sum
+ (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
+ doubleword in storage addressed by EA. (RS) [48:55] are
+ stored into bits 8:15 of the doubleword in storage
+ addressed by EA. (RS) [40:47] are stored into bits 16:23 of
+ the doubleword in storage addressed by EA. (RS) [32:39]
+ are stored into bits 23:31 of the doubleword in storage
+ addressed by EA. (RS) [24:31] are stored into bits 32:39 of
+ the doubleword in storage addressed by EA. (RS) [16:23]
+ are stored into bits 40:47 of the doubleword in storage
+ addressed by EA. (RS)[8:15] are stored into bits 48:55 of
+ the doubleword in storage addressed by EA. (RS) [0:7]
+ are stored into bits 56:63 of the doubleword in storage
+ addressed by EA.
+
Special Registers Altered:
None
r <- r + 1
EA <- EA + 4
+Description:
+
+ Let n = (32-RS). Let the effective address (EA) be the
+ sum (RA|0)+ D.
+
+ n consecutive words starting at EA are stored from the
+ low-order 32 bits of GPRs RS through 31.
+
+ This instruction is not supported in Little-Endian mode.
+ If it is executed in Little-Endian mode, the system align-
+ ment error handler is invoked.
+
Special Registers Altered:
None