bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / fixedstore.mdwn

diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
index ce64d4b9129ec3a5c3ddfc9edae459f05abf8bc8..94c419e35e23b1fb0ad0e39b4b3ee08d0b7bf66a 100644 (file)
--- a/openpower/isa/fixedstore.mdwn
+++ b/openpower/isa/fixedstore.mdwn
@@ -12,15 +12,6 @@
 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 
-<!-- MISSING stbh -->
-<!-- MISSING stbhx -->
-<!-- MISSING stbhu -->
-<!-- MISSING stbhux -->
-<!-- MISSING stbw -->
-<!-- MISSING stbwx -->
-<!-- MISSING stbwu -->
-<!-- MISSING stbwux -->
-
 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
 
 # Store Byte
@@ -33,7 +24,13 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + EXTS(D)
-    MEM(EA, 1) <- (RS)[56:63]
+    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
+
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ D.
+    RS[56:63] are stored into the byte in storage addressed
+    by EA.
 
 Special Registers Altered:
 
@@ -49,7 +46,13 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + (RB)
-    MEM(EA, 1) <- (RS)[56:63]
+    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
+
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
+    age addressed by EA.
 
 Special Registers Altered:
 
@@ -64,9 +67,19 @@ D-Form
 Pseudo-code:
 
     EA <- (RA) + EXTS(D)
-    MEM(EA, 1) <- (RS)[56:63]
+    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+    RS[56:63] are stored into the byte in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -80,9 +93,19 @@ X-Form
 Pseudo-code:
 
     EA <- (RA) + (RB)
-    MEM(EA, 1) <- (RS)[56:63]
+    MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    RS[56:63] are stored into the byte in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -97,7 +120,13 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + EXTS(D)
-    MEM(EA, 2) <- (RS)[48:63]
+    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
+
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ D.
+    RS[48:63] are stored into the halfword in storage
+    addressed by EA.
 
 Special Registers Altered:
 
@@ -113,7 +142,13 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + (RB)
-    MEM(EA, 2) <- (RS)[48:63]
+    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
+
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA|0)+ (RB). RS[48:63] are stored into the halfword in
+    storage addressed by EA.
 
 Special Registers Altered:
 
@@ -128,9 +163,19 @@ D-Form
 Pseudo-code:
 
     EA <- (RA) + EXTS(D)
-    MEM(EA, 2) <- (RS)[48:63]
+    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+    RS[48:63] are stored into the halfword in storage
+    addressed by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -144,9 +189,19 @@ X-Form
 Pseudo-code:
 
     EA <- (RA) + (RB)
-    MEM(EA, 2) <- (RS)[48:63]
+    MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    RS[48:63] are stored into the halfword in storage
+    addressed by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -161,7 +216,13 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + EXTS(D)
-    MEM(EA, 4) <- (RS)[32:63]
+    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
+
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ D.
+    RS[32:63] are stored into the word in storage addressed
+    by EA.
 
 Special Registers Altered:
 
@@ -177,7 +238,13 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + (RB)
-    MEM(EA, 4) <- (RS)[32:63]
+    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
+
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA|0)+ (RB). RS[32:63] are stored into the word in stor-
+    age addressed by EA.
 
 Special Registers Altered:
 
@@ -192,9 +259,19 @@ D-Form
 Pseudo-code:
 
     EA <- (RA) + EXTS(D)
-    MEM(EA, 4) <- (RS)[32:63]
+    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+    RS[32:63] are stored into the word in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -208,9 +285,19 @@ X-Form
 Pseudo-code:
 
     EA <- (RA) + (RB)
-    MEM(EA, 4) <- (RS)[32:63]
+    MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    RS[32:63] are stored into the word in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -231,6 +318,12 @@ Pseudo-code:
     EA <- b + EXTS(DS || 0b00)
     MEM(EA, 8) <- (RS)
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA|0)+ (DS||0b00). (RS) is stored into the doubleword
+    in storage addressed by EA.
+
 Special Registers Altered:
 
     None
@@ -247,6 +340,12 @@ Pseudo-code:
     EA <- b + (RB)
     MEM(EA, 8) <- (RS)
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA|0)+ (RB). (RS) is stored into the doubleword in
+    storage addressed by EA.
+
 Special Registers Altered:
 
     None
@@ -263,6 +362,16 @@ Pseudo-code:
     MEM(EA, 8) <- (RS)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA)+ (DS||0b00). (RS) is stored into the doubleword in
+    storage addressed by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -279,6 +388,16 @@ Pseudo-code:
     MEM(EA, 8) <- (RS)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    (RS) is stored into the doubleword in storage
+    addressed by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -307,6 +426,25 @@ Pseudo-code:
     EA <- b + EXTS(DS || 0b00)
     MEM(EA, 16) <- RSp
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+
+    (DS||0b00). The contents of register pair RSp are
+    stored into the quadword in storage addressed by EA.
+
+    If RSp is odd, the instruction form is invalid.
+
+    The contents of an even-odd pair of GPRs is stored into
+    the quadword in storage addressed by EA as follows.
+    In Big-Endian mode, the even-numbered GPR is stored
+    into the doubleword in storage addressed by EA and
+    the odd-numbered GPR is stored into the doubleword
+    addressed by EA+8. In Little-Endian mode, the
+    even-numbered GPR is stored byte-reversed into the
+    doubleword in storage addressed by EA+8 and the
+    odd-numbered GPR is stored byte-reversed into the
+    doubleword addressed by EA.
+
 Special Registers Altered:
 
     None
@@ -325,6 +463,14 @@ Pseudo-code:
     EA <- b + (RB)
     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA|0)+ (RB). (RS)56:63 are stored into bits 0:7 of the
+    halfword in storage addressed by EA. (RS) 48:55 are
+    stored into bits 8:15 of the halfword in storage
+    addressed by EA.
+
 Special Registers Altered:
 
     None
@@ -342,6 +488,16 @@ Pseudo-code:
     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
                    ||(RS)[32:39])
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
+    word in storage addressed by EA. (RS) [48:55] are stored
+    into bits 8:15 of the word in storage addressed by EA.
+    (RS)[40:47] are stored into bits 16:23 of the word in stor-
+    age addressed by EA. (RS) [32:39] are stored into bits
+    24:31 of the word in storage addressed by EA.
+
 Special Registers Altered:
 
     None
@@ -363,6 +519,23 @@ Pseudo-code:
                     || (RS)[24:31] || (RS)[16:23]
                     || (RS)[8:15]  || (RS)[0:7])
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
+    doubleword in storage addressed by EA. (RS) [48:55] are
+    stored into bits 8:15 of the doubleword in storage
+    addressed by EA. (RS) [40:47] are stored into bits 16:23 of
+    the doubleword in storage addressed by EA. (RS) [32:39]
+    are stored into bits 23:31 of the doubleword in storage
+    addressed by EA. (RS) [24:31] are stored into bits 32:39 of
+    the doubleword in storage addressed by EA. (RS) [16:23]
+    are stored into bits 40:47 of the doubleword in storage
+    addressed by EA. (RS)[8:15] are stored into bits 48:55 of
+    the doubleword in storage addressed by EA. (RS) [0:7]
+    are stored into bits 56:63 of the doubleword in storage
+    addressed by EA.
+
 Special Registers Altered:
 
     None
@@ -380,12 +553,24 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + EXTS(D)
-    r <- RS
+    r <- RS[0:63]
     do while r <= 31
         MEM(EA, 4) <- GPR(r)[32:63]
         r <-  r + 1
         EA <-  EA + 4
 
+Description:
+
+    Let n = (32-RS). Let the effective address (EA) be the
+    sum (RA|0)+ D.
+
+    n consecutive words starting at EA are stored from the
+    low-order 32 bits of GPRs RS through 31.
+
+    This instruction is not supported in Little-Endian mode.
+    If it is executed in Little-Endian mode, the system align-
+    ment error handler is invoked.
+
 Special Registers Altered:
 
     None