added stdsux instruction

[openpower-isa.git] / openpower / isa / fixedstoreshift.mdwn

diff --git a/openpower/isa/fixedstoreshift.mdwn b/openpower/isa/fixedstoreshift.mdwn
index 1f377cd1c58afefc573b85cc0cd30c34bd6be118..44349e9a9850b3b9c5ba28fd6ab75d505f6f858a 100644 (file)
--- a/openpower/isa/fixedstoreshift.mdwn
+++ b/openpower/isa/fixedstoreshift.mdwn
@@ -110,16 +110,16 @@ Special Registers Altered:
 
     None
 
-# Store Word Indexed
+# Store Word Shifted Indexed
 
 X-Form
 
-* stwx RS,RA,RB
+* stwsx RS,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) << (SH+1)
     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 
 Description:
@@ -132,15 +132,15 @@ Special Registers Altered:
 
     None
 
-# Store Word with Update Indexed
+# Store Word Shifted with Update Indexed
 
 X-Form
 
-* stwux RS,RA,RB
+* stwsux RS,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB) << (SH+1)
     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
 
@@ -162,16 +162,16 @@ Special Registers Altered:
 
 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
 
-# Store Doubleword Indexed
+# Store Doubleword Shifted Indexed
 
 X-Form
 
-* stdx RS,RA,RB
+* stdsx RS,RA,RB,SH
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) << (SH+1)
     MEM(EA, 8) <- (RS)
 
 Description:
@@ -184,15 +184,15 @@ Special Registers Altered:
 
     None
 
-# Store Doubleword with Update Indexed
+# Store Doubleword Shifted with Update Indexed
 
 X-Form
 
-* stdux RS,RA,RB
+* stdsux RS,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB) << (SH+1)
     MEM(EA, 8) <- (RS)
     RA <- EA