fixedsync.mdwn: change sync from v3.1B version to v3.0B version

[openpower-isa.git] / openpower / isa / fixedsync.mdwn

diff --git a/openpower/isa/fixedsync.mdwn b/openpower/isa/fixedsync.mdwn
index 979a6074988aba99fbadb12f4810cbb21b1c9f52..b9786f497b5ec3ad8ce6e05ac461d31a4c1be77c 100644 (file)
--- a/openpower/isa/fixedsync.mdwn
+++ b/openpower/isa/fixedsync.mdwn
@@ -8,6 +8,21 @@ XL-Form
 
 * isync
 
+Pseudo-code:
+
+    # TODO
+    undefined(0)
+
+Special Registers Altered:
+
+    None
+
+# Synchronise
+
+XL-Form
+
+* sync L2
+
 Pseudo-code:
 
     # TODO
@@ -25,8 +40,11 @@ X-Form
 
 Pseudo-code:
 
-    # TODO
-    undefined(0)
+    EA <- (RA|0) + (RB)
+    RESERVE <- 1
+    RESERVE_LENGTH <- 1
+    RESERVE_ADDR <- real_addr(EA)
+    RT <- [0]*56 || MEM(EA, 1)
 
 Special Registers Altered:
 
@@ -40,8 +58,11 @@ X-Form
 
 Pseudo-code:
 
-    # TODO
-    undefined(0)
+    EA <- (RA|0) + (RB)
+    RESERVE <- 1
+    RESERVE_LENGTH <- 2
+    RESERVE_ADDR <- real_addr(EA)
+    RT <- [0]*48 || MEM(EA, 2)
 
 Special Registers Altered:
 
@@ -73,8 +94,29 @@ X-Form
 
 Pseudo-code:
 
-    # TODO
-    undefined(0)
+    EA <- (RA|0) + (RB)
+    RESERVE <- 1
+    RESERVE_LENGTH <- 8
+    RESERVE_ADDR <- real_addr(EA)
+    RT <- MEM(EA, 8)
+
+Special Registers Altered:
+
+    None
+
+# Load Quadword And Reserve Indexed
+
+X-Form
+
+* lqarx RTp,RA,RB,EH
+
+Pseudo-code:
+
+    EA <- (RA|0) + (RB)
+    RESERVE <- 1
+    RESERVE_LENGTH <- 16
+    RESERVE_ADDR <- real_addr(EA)
+    RTp <- MEM(EA, 16)
 
 Special Registers Altered:
 
@@ -88,8 +130,35 @@ X-Form
 
 Pseudo-code:
 
-    # TODO
-    undefined(0)
+    EA <- (RA|0) + (RB)
+    undefined_case <- 0
+    store_performed <- 0b0
+    if RESERVE then
+        if ((RESERVE_LENGTH = 1) &
+           (RESERVE_ADDR = real_addr(EA))) then
+            MEM(EA, 1) <- (RS)[56:63]
+            undefined_case <- 0
+            store_performed <- 0b1
+        else
+            # set z to smallest real page size supported by implementation
+            z <- REAL_PAGE_SIZE
+            if (RESERVE_ADDR / z) = (real_addr(EA) / z) then
+                undefined_case <- 1
+            else
+                undefined_case <- 0
+                store_performed <- 0b0
+    else
+        undefined_case <- 0
+        store_performed <- 0b0
+    if undefined_case then
+        u1 <- undefined(0b1)
+        if u1 then
+            MEM(EA, 1) <- (RS)[56:63]
+        u2 <- undefined(0b1)
+        CR0 <- 0b00 || u2 || XER[SO]
+    else
+        CR0 <- 0b00 || store_performed || XER[SO]
+    RESERVE <- 0
 
 Special Registers Altered:
 
@@ -103,8 +172,35 @@ X-Form
 
 Pseudo-code:
 
-    # TODO
-    undefined(0)
+    EA <- (RA|0) + (RB)
+    undefined_case <- 0
+    store_performed <- 0b0
+    if RESERVE then
+        if ((RESERVE_LENGTH = 2) &
+           (RESERVE_ADDR = real_addr(EA))) then
+            MEM(EA, 2) <- (RS)[48:63]
+            undefined_case <- 0
+            store_performed <- 0b1
+        else
+            # set z to smallest real page size supported by implementation
+            z <- REAL_PAGE_SIZE
+            if (RESERVE_ADDR / z) = (real_addr(EA) / z) then
+                undefined_case <- 1
+            else
+                undefined_case <- 0
+                store_performed <- 0b0
+    else
+        undefined_case <- 0
+        store_performed <- 0b0
+    if undefined_case then
+        u1 <- undefined(0b1)
+        if u1 then
+            MEM(EA, 2) <- (RS)[48:63]
+        u2 <- undefined(0b1)
+        CR0 <- 0b00 || u2 || XER[SO]
+    else
+        CR0 <- 0b00 || store_performed || XER[SO]
+    RESERVE <- 0
 
 Special Registers Altered:
 
@@ -120,34 +216,34 @@ Pseudo-code:
 
     EA <- (RA|0) + (RB)
     undefined_case <- 0
-    store_performed <- 0
+    store_performed <- 0b0
     if RESERVE then
-      if (RESERVE_LENGTH = 4 &
-         RESERVE_ADDR = real_addr(EA)) then
-           MEM(EA, 1) <- (RS)[32:63]
-           undefined_case <- 0
-           store_performed <- 1
-      else
-           z <- REAL_PAGE_SIZE # smallest implementation's real page size 
-           if RESERVE_ADDR / z = real_addr(EA) / z then
-              undefined_case <- 1
-           else
-             undefined_case <- 0
-             store_performed <- 0
+        if ((RESERVE_LENGTH = 4) &
+           (RESERVE_ADDR = real_addr(EA))) then
+            MEM(EA, 4) <- (RS)[32:63]
+            undefined_case <- 0
+            store_performed <- 0b1
+        else
+            # set z to smallest real page size supported by implementation
+            z <- REAL_PAGE_SIZE
+            if (RESERVE_ADDR / z) = (real_addr(EA) / z) then
+                undefined_case <- 1
+            else
+                undefined_case <- 0
+                store_performed <- 0b0
     else
-      undefined_case <- 0
-      store_performed <- 0
+        undefined_case <- 0
+        store_performed <- 0b0
     if undefined_case then
-      u1 <- undefined(0b1)
-      if u1 then
-         MEM(EA, 1) <- (RS)[32:63]
-      u2 <- undefined(0b0)
-      CR0 <- 0b00 || u2 || XER[SO]
+        u1 <- undefined(0b1)
+        if u1 then
+            MEM(EA, 4) <- (RS)[32:63]
+        u2 <- undefined(0b1)
+        CR0 <- 0b00 || u2 || XER[SO]
     else
-      CR0 <- 0b00 || store_performed || XER[SO]
+        CR0 <- 0b00 || store_performed || XER[SO]
     RESERVE <- 0
 
-
 Special Registers Altered:
 
     CR0
@@ -160,10 +256,78 @@ X-Form
 
 Pseudo-code:
 
-    # TODO
-    undefined(0)
+    EA <- (RA|0) + (RB)
+    undefined_case <- 0
+    store_performed <- 0b0
+    if RESERVE then
+        if ((RESERVE_LENGTH = 8) &
+           (RESERVE_ADDR = real_addr(EA))) then
+            MEM(EA, 8) <- (RS)
+            undefined_case <- 0
+            store_performed <- 0b1
+        else
+            # set z to smallest real page size supported by implementation
+            z <- REAL_PAGE_SIZE
+            if (RESERVE_ADDR / z) = (real_addr(EA) / z) then
+                undefined_case <- 1
+            else
+                undefined_case <- 0
+                store_performed <- 0b0
+    else
+        undefined_case <- 0
+        store_performed <- 0b0
+    if undefined_case then
+        u1 <- undefined(0b1)
+        if u1 then
+            MEM(EA, 8) <- (RS)
+        u2 <- undefined(0b1)
+        CR0 <- 0b00 || u2 || XER[SO]
+    else
+        CR0 <- 0b00 || store_performed || XER[SO]
+    RESERVE <- 0
 
 Special Registers Altered:
 
     CR0
 
+# Store Quadword Conditional Indexed
+
+X-Form
+
+* stqcx. RSp,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA|0) + (RB)
+    undefined_case <- 0
+    store_performed <- 0b0
+    if RESERVE then
+        if ((RESERVE_LENGTH = 16) &
+           (RESERVE_ADDR = real_addr(EA))) then
+            MEM(EA, 16) <- (RSp)
+            undefined_case <- 0
+            store_performed <- 0b1
+        else
+            # set z to smallest real page size supported by implementation
+            z <- REAL_PAGE_SIZE
+            if (RESERVE_ADDR / z) = (real_addr(EA) / z) then
+                undefined_case <- 1
+            else
+                undefined_case <- 0
+                store_performed <- 0b0
+    else
+        undefined_case <- 0
+        store_performed <- 0b0
+    if undefined_case then
+        u1 <- undefined(0b1)
+        if u1 then
+            MEM(EA, 16) <- (RSp)
+        u2 <- undefined(0b1)
+        CR0 <- 0b00 || u2 || XER[SO]
+    else
+        CR0 <- 0b00 || store_performed || XER[SO]
+    RESERVE <- 0
+
+Special Registers Altered:
+
+    CR0