bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / fparith.mdwn

diff --git a/openpower/isa/fparith.mdwn b/openpower/isa/fparith.mdwn
index a6a5e91a487504d11aab76e3bf1e807c9a8bb60c..3a238005f0b331247ceb74be012a6e114d19d227 100644 (file)
--- a/openpower/isa/fparith.mdwn
+++ b/openpower/isa/fparith.mdwn
@@ -7,7 +7,7 @@
 A-Form
 
 * fadds FRT,FRA,FRB (Rc=0)
-* fadds. FRT,FRA,FRB (Rc=0)
+* fadds. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -25,7 +25,7 @@ Special Registers Altered:
 A-Form
 
 * fadd FRT,FRA,FRB (Rc=0)
-* fadd. FRT,FRA,FRB (Rc=0)
+* fadd. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -43,7 +43,7 @@ Special Registers Altered:
 A-Form
 
 * fsubs FRT,FRA,FRB (Rc=0)
-* fsubs. FRT,FRA,FRB (Rc=0)
+* fsubs. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -61,7 +61,7 @@ Special Registers Altered:
 A-Form
 
 * fsub FRT,FRA,FRB (Rc=0)
-* fsub. FRT,FRA,FRB (Rc=0)
+* fsub. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -79,7 +79,7 @@ Special Registers Altered:
 A-Form
 
 * fmuls FRT,FRA,FRC (Rc=0)
-* fmuls. FRT,FRA,FRC (Rc=0)
+* fmuls. FRT,FRA,FRC (Rc=1)
 
 Pseudo-code:
 
@@ -97,7 +97,7 @@ Special Registers Altered:
 A-Form
 
 * fmul FRT,FRA,FRC (Rc=0)
-* fmul. FRT,FRA,FRC (Rc=0)
+* fmul. FRT,FRA,FRC (Rc=1)
 
 Pseudo-code:
 
@@ -115,7 +115,7 @@ Special Registers Altered:
 A-Form
 
 * fdivs FRT,FRA,FRB (Rc=0)
-* fdivs. FRT,FRA,FRB (Rc=0)
+* fdivs. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -133,7 +133,7 @@ Special Registers Altered:
 A-Form
 
 * fdiv FRT,FRA,FRB (Rc=0)
-* fdiv. FRT,FRA,FRB (Rc=0)
+* fdiv. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -151,7 +151,7 @@ Special Registers Altered:
 A-Form
 
 * fmadds FRT,FRA,FRC,FRB (Rc=0)
-* fmadds. FRT,FRA,FRC,FRB (Rc=0)
+* fmadds. FRT,FRA,FRC,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -169,7 +169,7 @@ Special Registers Altered:
 A-Form
 
 * fmsubs FRT,FRA,FRC,FRB (Rc=0)
-* fmsubs. FRT,FRA,FRC,FRB (Rc=0)
+* fmsubs. FRT,FRA,FRC,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -187,11 +187,11 @@ Special Registers Altered:
 A-Form
 
 * fnmadds FRT,FRA,FRC,FRB (Rc=0)
-* fnmadds. FRT,FRA,FRC,FRB (Rc=0)
+* fnmadds. FRT,FRA,FRC,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
+    FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
 
 Special Registers Altered:
 
@@ -205,11 +205,11 @@ Special Registers Altered:
 A-Form
 
 * fnmsubs FRT,FRA,FRC,FRB (Rc=0)
-* fnmsubs. FRT,FRA,FRC,FRB (Rc=0)
+* fnmsubs. FRT,FRA,FRC,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
+    FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
 
 Special Registers Altered: