bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / fpload.mdwn

diff --git a/openpower/isa/fpload.mdwn b/openpower/isa/fpload.mdwn
index 9e16cc9ed96e8a261d69912a35edca57491b5525..c849ca8fc17ef3627af9a1787ac175f7d514151e 100644 (file)
--- a/openpower/isa/fpload.mdwn
+++ b/openpower/isa/fpload.mdwn
@@ -16,6 +16,7 @@ Pseudo-code:
 Description:
 
     Let the effective address (EA) be the sum (RA|0)+D.
+
     The word in storage addressed by EA is interpreted as
     a floating-point single-precision operand. This word is
     converted to floating-point double format (see
@@ -61,6 +62,19 @@ Pseudo-code:
     FRT <- DOUBLE(MEM(EA, 4))
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+D.
+
+    The word in storage addressed by EA is interpreted as
+    a floating-point single-precision operand. This word is
+    converted to floating-point double format (see
+    page 138) and placed into register FRT.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -77,6 +91,19 @@ Pseudo-code:
     FRT <- DOUBLE(MEM(EA, 4))
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+(RB).
+
+    The word in storage addressed by EA is interpreted as
+    a floating-point single-precision operand. This word is
+    converted to floating-point double format (see
+    page 138) and placed into register FRT.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -92,6 +119,13 @@ Pseudo-code:
     EA <- (RA|0) + EXTS(D)
     FRT <- MEM(EA, 8)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+D.
+
+    The doubleword in storage addressed by EA is loaded
+    into register FRT.
+
 Special Registers Altered:
 
     None
@@ -107,6 +141,13 @@ Pseudo-code:
     EA <- (RA|0) + (RB)
     FRT <- MEM(EA, 8)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+(RB).
+
+    The doubleword in storage addressed by EA is loaded
+    into register FRT.
+
 Special Registers Altered:
 
     None
@@ -123,6 +164,17 @@ Pseudo-code:
     FRT <- MEM(EA, 8)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+D.
+
+    The doubleword in storage addressed by EA is loaded
+    into register FRT.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -139,6 +191,17 @@ Pseudo-code:
     FRT <- MEM(EA, 8)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+(RB).
+
+    The doubleword in storage addressed by EA is loaded
+    into register FRT.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -154,6 +217,14 @@ Pseudo-code:
     EA <- (RA|0) + (RB)
     FRT <- EXTS(MEM(EA, 4))
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+(RB).
+
+    The word in storage addressed by EA is loaded into
+    FRT [32:63]. FRT [0:31] are filled with a copy of bit 0 of the
+    loaded word.
+
 Special Registers Altered:
 
     None
@@ -169,6 +240,13 @@ Pseudo-code:
     EA <- (RA|0) + (RB)
     FRT <- [0]*32 || MEM(EA, 4)
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+(RB).
+
+    The word in storage addressed by EA is loaded into
+    FRT [32:63]. FRT [0:31] are set to 0.
+
 Special Registers Altered:
 
     None