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[openpower-isa.git] / openpower / isa / fpstore.mdwn

diff --git a/openpower/isa/fpstore.mdwn b/openpower/isa/fpstore.mdwn
index 6103753a2e58afafc59df9a6f03d5b50f36d20d3..3d7bd7763d716d6b0b4da61f51c3acfff624870f 100644 (file)
--- a/openpower/isa/fpstore.mdwn
+++ b/openpower/isa/fpstore.mdwn
@@ -60,6 +60,18 @@ Pseudo-code:
     MEM(EA, 4)<- SINGLE( (FRS) )
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA) +D.
+
+    The contents of register FRS are converted to single
+    format (see page 142) and stored into the word in stor-
+    age addressed by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -76,6 +88,18 @@ Pseudo-code:
     MEM(EA, 4)<- SINGLE( (FRS) )
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA) +(RB).
+
+    The contents of register FRS are converted to single
+    format (see page 142) and stored into the word in stor-
+    age addressed by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -91,6 +115,13 @@ Pseudo-code:
     EA <- (RA|0) + EXTS(D)
     MEM(EA, 8)<- (FRS) 
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+D.
+
+    The contents of register FRS are stored into the dou-
+    bleword in storage addressed by EA.
+
 Special Registers Altered:
 
     None
@@ -106,6 +137,13 @@ Pseudo-code:
     EA <- (RA|0) + (RB)
     MEM(EA, 8)<- (FRS) 
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+(RB).
+
+    The contents of register FRS are stored into the dou-
+    bleword in storage addressed by EA.
+
 Special Registers Altered:
 
     None
@@ -122,6 +160,17 @@ Pseudo-code:
     MEM(EA, 8)<- (FRS) 
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+D.
+
+    The contents of register FRS are stored into the dou-
+    bleword in storage addressed by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -138,6 +187,17 @@ Pseudo-code:
     MEM(EA, 8)<- (FRS) 
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+(RB).
+
+    The contents of register FRS are stored into the dou-
+    bleword in storage addressed by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -154,6 +214,25 @@ Pseudo-code:
     EA <- b + (RB)
     MEM(EA, 8)<- (FRS)[32:63]
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+(RB).
+
+    (FRS)[32:63] are stored, without conversion, into the word
+    in storage addressed by EA.
+
+    If the contents of register FRS were produced, either
+    directly or indirectly, by a Load Floating-Point Single
+    instruction, a single-precision Arithmetic instruction, or
+    frsp, then the value stored is undefined. (The contents
+    of register FRS are produced directly by such an
+    instruction if FRS is the target register for the instruc-
+    tion. The contents of register FRS are produced indi-
+    rectly by such an instruction if FRS is the final target
+    register of a sequence of one or more Floating-Point
+    Move instructions, with the input to the sequence hav-
+    ing been produced directly by such an instruction.)
+
 Special Registers Altered:
 
     None