added english language description for lwzsx instruction

[openpower-isa.git] / openpower / isa / pifixedload.mdwn

diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn
index a9f67ebf5d541655dbc1d63e8741d2e8e33db979..0418b1cd4e89ec350842d373190343fcd1c72893 100644 (file)
--- a/openpower/isa/pifixedload.mdwn
+++ b/openpower/isa/pifixedload.mdwn
@@ -186,7 +186,6 @@ Description:
 
     If RA=0 or RA=RT, the instruction form is invalid.
 
-
 Special Registers Altered:
 
     None
@@ -203,6 +202,16 @@ Pseudo-code:
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -219,6 +228,16 @@ Pseudo-code:
     RT <- EXTS(MEM(EA, 4))
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are filled with a copy of bit 0 of the loaded word.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -235,6 +254,15 @@ Pseudo-code:
     RT <- MEM(EA, 8)
     RA <- (RA) + EXTS(DS || 0b00)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The doubleword in storage addressed by EA is loaded into RT.
+
+    The sum (RA)+ (DS||0b00) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -251,6 +279,16 @@ Pseudo-code:
     RT <- MEM(EA, 8)
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The doubleword in storage addressed by EA is loaded
+    into RT.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None