added english language description for lwzsx instruction

[openpower-isa.git] / openpower / isa / pifixedload.mdwn

diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn
index b5671cbc25ae87b174b8e0c2832d9cd4d61a479d..0418b1cd4e89ec350842d373190343fcd1c72893 100644 (file)
--- a/openpower/isa/pifixedload.mdwn
+++ b/openpower/isa/pifixedload.mdwn
@@ -20,6 +20,16 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- (RA) + EXTS(D)
 
+Description:
+
+    Let the effective address (EA) be register RA. 
+    The byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
+
+    The sum (RA) + D is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -36,6 +46,16 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be register RA.
+    The byte in storage addressed by EA is loaded into RT[56:63]. 
+    RT[0:55] are set to 0.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -52,6 +72,16 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- (RA) + EXTS(D)
 
+Description:
+
+    Let the effective address (EA) be register RA. 
+    The halfword in storage addressed by EA is loaded into RT[48:63]. 
+    RT[0:47] are set to 0.
+
+    The sum (RA) + D is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -68,6 +98,16 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63]. 
+    RT[0:47] are set to 0.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -84,6 +124,16 @@ Pseudo-code:
     RT <- EXTS(MEM(EA, 2))
     RA <- (RA) + EXTS(D)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    The sum (RA) + D is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -100,6 +150,16 @@ Pseudo-code:
     RT <- EXTS(MEM(EA, 2))
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -116,6 +176,16 @@ Pseudo-code:
     RT <- [0]*32 || MEM(EA, 4)
     RA <- (RA) + EXTS(D)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    The sum (RA) + D is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -132,6 +202,16 @@ Pseudo-code:
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -148,6 +228,16 @@ Pseudo-code:
     RT <- EXTS(MEM(EA, 4))
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are filled with a copy of bit 0 of the loaded word.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -164,6 +254,15 @@ Pseudo-code:
     RT <- MEM(EA, 8)
     RA <- (RA) + EXTS(DS || 0b00)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The doubleword in storage addressed by EA is loaded into RT.
+
+    The sum (RA)+ (DS||0b00) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -180,6 +279,16 @@ Pseudo-code:
     RT <- MEM(EA, 8)
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The doubleword in storage addressed by EA is loaded
+    into RT.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None