bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / pifixedloadshift.mdwn

diff --git a/openpower/isa/pifixedloadshift.mdwn b/openpower/isa/pifixedloadshift.mdwn
index 1572acc7d445d33dd3e0d7074cdd3652b2beb3b5..75a9a25b42e6766a10c3b5b0e279fbceeaf86663 100644 (file)
--- a/openpower/isa/pifixedloadshift.mdwn
+++ b/openpower/isa/pifixedloadshift.mdwn
@@ -15,17 +15,18 @@
 
 X-Form
 
-* lbzupsx RT,RA,RB
+* lbzupsx RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA)
+    EA <- (RA)<<(SH+1)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- (RA) + (RB)
 
 Description:
 
-    Let the effective address (EA) be register RA.
+    Let the effective address (EA) be the contents of
+    register RA shifted by (SH+1).
 
     The byte in storage addressed by EA is loaded into RT[56:63]. 
     RT[0:55] are set to 0.
@@ -42,17 +43,19 @@ Special Registers Altered:
 
 X-Form
 
-* lhzupsx RT,RA,RB
+* lhzupsx RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA)
+    EA <- (RA)<<(SH+1)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- (RA) + (RB)
 
 Description:
 
-    Let the effective address (EA) be register RA.
+    Let the effective address (EA) be the contents of
+    register RA shifted by (SH+1).
+
     The halfword in storage addressed by EA is loaded into RT[48:63]. 
     RT[0:47] are set to 0.
 
@@ -68,17 +71,18 @@ Special Registers Altered:
 
 X-Form
 
-* lhaupsx RT,RA,RB
+* lhaupsx RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA)
+    EA <- (RA)<<(SH+1)
     RT <- EXTS(MEM(EA, 2))
     RA <- (RA) + (RB)
 
 Description:
 
-    Let the effective address (EA) be the register RA.
+    Let the effective address (EA) be the contents of
+    register RA shifted by (SH+1).
 
     The halfword in storage addressed by EA is loaded into RT[48:63].
     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
@@ -95,17 +99,18 @@ Special Registers Altered:
 
 X-Form
 
-* lwzupsx RT,RA,RB
+* lwzupsx RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA)
+    EA <- (RA)<<(SH+1)
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- (RA) + (RB)
 
 Description:
 
-    Let the effective address (EA) be the register RA.
+    Let the effective address (EA) be the contents of
+    register RA shifted by (SH+1).
 
     The halfword in storage addressed by EA is loaded into RT[48:63].
     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
@@ -122,17 +127,18 @@ Special Registers Altered:
 
 X-Form
 
-* lwaupsx RT,RA,RB
+* lwaupsx RT,RA,RB.SH
 
 Pseudo-code:
 
-    EA <- (RA)
+    EA <- (RA)<<(SH+1)
     RT <- EXTS(MEM(EA, 4))
     RA <- (RA) + (RB)
 
 Description:
 
-    Let the effective address (EA) be the register RA.
+    Let the effective address (EA) be the contents of
+    register RA shifted by (SH+1).
 
     The word in storage addressed by EA is loaded into RT[32:63].
     RT[0:31] are filled with a copy of bit 0 of the loaded word.
@@ -149,17 +155,18 @@ Special Registers Altered:
 
 X-Form
 
-* ldupsx RT,RA,RB
+* ldupsx RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA)
+    EA <- (RA)<<(SH+1)
     RT <- MEM(EA, 8)
     RA <- (RA) + (RB)
 
 Description:
 
-    Let the effective address (EA) be the register RA.
+    Let the effective address (EA) be the contents of
+    register RA shifted by (SH+1).
 
     The doubleword in storage addressed by EA is loaded into RT.