Added English Language description for stwup instruction

[openpower-isa.git] / openpower / isa / pifixedstore.mdwn

diff --git a/openpower/isa/pifixedstore.mdwn b/openpower/isa/pifixedstore.mdwn
index a8060e56086da1d1a2716b8cda813d16580c4e5c..8a45cd96858ca026ec0957baa7f2b50ec6c111c9 100644 (file)
--- a/openpower/isa/pifixedstore.mdwn
+++ b/openpower/isa/pifixedstore.mdwn
@@ -7,15 +7,25 @@
 
 D-Form
 
-* stbu RS,D(RA)
+* stbup RS,D(RA)
 
 Pseudo-code:
 
     EA <- (RA) + EXTS(D)
     ea <- (RA)
-    MEM(ra, 1) <- (RS)[XLEN-8:XLEN-1]
+    MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+    (RS)[56:63] are stored into the byte in storage addressed
+    by EA. 
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -24,7 +34,7 @@ Special Registers Altered:
 
 X-Form
 
-* stbux RS,RA,RB
+* stbupx RS,RA,RB
 
 Pseudo-code:
 
@@ -33,6 +43,16 @@ Pseudo-code:
     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    (RS)[56:63] are stored into the byte in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -41,7 +61,7 @@ Special Registers Altered:
 
 D-Form
 
-* sthu RS,D(RA)
+* sthup RS,D(RA)
 
 Pseudo-code:
 
@@ -50,6 +70,12 @@ Pseudo-code:
     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ D.
+    (RS)[48:63] are stored into the halfword in storage
+    addressed by EA.
+
 Special Registers Altered:
 
     None
@@ -58,7 +84,7 @@ Special Registers Altered:
 
 X-Form
 
-* sthux RS,RA,RB
+* sthupx RS,RA,RB
 
 Pseudo-code:
 
@@ -67,6 +93,16 @@ Pseudo-code:
     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    (RS)[56:63] are stored into the byte in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid
+
 Special Registers Altered:
 
     None
@@ -75,7 +111,7 @@ Special Registers Altered:
 
 D-Form
 
-* stwu RS,D(RA)
+* stwup RS,D(RA)
 
 Pseudo-code:
 
@@ -84,6 +120,16 @@ Pseudo-code:
     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+    (RS)[32:63] are stored into the word in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
@@ -92,7 +138,7 @@ Special Registers Altered:
 
 X-Form
 
-* stwux RS,RA,RB
+* stwupx RS,RA,RB
 
 Pseudo-code:
 
@@ -109,7 +155,7 @@ Special Registers Altered:
 
 DS-Form
 
-* stdu RS,DS(RA)
+* stdup RS,DS(RA)
 
 Pseudo-code:
 
@@ -126,7 +172,7 @@ Special Registers Altered:
 
 X-Form
 
-* stdux RS,RA,RB
+* stdupx RS,RA,RB
 
 Pseudo-code: