added stdsux instruction

[openpower-isa.git] / openpower / isa / pifixedstore.mdwn

diff --git a/openpower/isa/pifixedstore.mdwn b/openpower/isa/pifixedstore.mdwn
index a8060e56086da1d1a2716b8cda813d16580c4e5c..dfccc4955c889afeee1904ca7623cdead9c6413b 100644 (file)
--- a/openpower/isa/pifixedstore.mdwn
+++ b/openpower/isa/pifixedstore.mdwn
@@ -3,28 +3,39 @@
 <!-- This defines instructions that store from a register to RAM -->
 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
 
-# Store Byte with Update
+# Store Byte with Post-Update
 
 D-Form
 
-* stbu RS,D(RA)
+* stbup RS,D(RA)
 
 Pseudo-code:
 
     EA <- (RA) + EXTS(D)
     ea <- (RA)
-    MEM(ra, 1) <- (RS)[XLEN-8:XLEN-1]
+    MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+
+    (RS)[56:63] are stored into the byte in storage addressed
+    by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
 
-# Store Byte with Update Indexed
+# Store Byte with Post-Update Indexed
 
 X-Form
 
-* stbux RS,RA,RB
+* stbupx RS,RA,RB
 
 Pseudo-code:
 
@@ -33,15 +44,26 @@ Pseudo-code:
     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    (RS)[56:63] are stored into the byte in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
 
-# Store Halfword with Update
+# Store Halfword with Post-Update
 
 D-Form
 
-* sthu RS,D(RA)
+* sthup RS,D(RA)
 
 Pseudo-code:
 
@@ -50,15 +72,22 @@ Pseudo-code:
     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ D.
+
+    (RS)[48:63] are stored into the halfword in storage
+    addressed by EA.
+
 Special Registers Altered:
 
     None
 
-# Store Halfword with Update Indexed
+# Store Halfword with Post-Update Indexed
 
 X-Form
 
-* sthux RS,RA,RB
+* sthupx RS,RA,RB
 
 Pseudo-code:
 
@@ -67,15 +96,26 @@ Pseudo-code:
     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    (RS)[56:63] are stored into the byte in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid
+
 Special Registers Altered:
 
     None
 
-# Store Word with Update
+# Store Word with Post-Update
 
 D-Form
 
-* stwu RS,D(RA)
+* stwup RS,D(RA)
 
 Pseudo-code:
 
@@ -84,15 +124,26 @@ Pseudo-code:
     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+
+    (RS)[32:63] are stored into the word in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
 
-# Store Word with Update Indexed
+# Store Word with Post-Update Indexed
 
 X-Form
 
-* stwux RS,RA,RB
+* stwupx RS,RA,RB
 
 Pseudo-code:
 
@@ -101,15 +152,26 @@ Pseudo-code:
     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    (RS)[32:63] are stored into the word in storage addressed
+    by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
 
-# Store Doubleword with Update
+# Store Doubleword with Post-Update
 
 DS-Form
 
-* stdu RS,DS(RA)
+* stdup RS,DS(RA)
 
 Pseudo-code:
 
@@ -118,15 +180,26 @@ Pseudo-code:
     MEM(ea, 8) <- (RS)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum.
+
+    (RA)+ (DS||0b00). (RS) is stored into the doubleword in
+    storage addressed by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
 
-# Store Doubleword with Update Indexed
+# Store Doubleword with Post-Update Indexed
 
 X-Form
 
-* stdux RS,RA,RB
+* stdupx RS,RA,RB
 
 Pseudo-code:
 
@@ -135,6 +208,17 @@ Pseudo-code:
     MEM(ea, 8) <- (RS)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    (RS) is stored into the doubleword in storage
+    addressed by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None