bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / pifixedstore.mdwn

diff --git a/openpower/isa/pifixedstore.mdwn b/openpower/isa/pifixedstore.mdwn
index ec2a0e3f07914f2dafac19eb952f4f25843d0719..dfccc4955c889afeee1904ca7623cdead9c6413b 100644 (file)
--- a/openpower/isa/pifixedstore.mdwn
+++ b/openpower/isa/pifixedstore.mdwn
@@ -3,7 +3,7 @@
 <!-- This defines instructions that store from a register to RAM -->
 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
 
-# Store Byte with Update
+# Store Byte with Post-Update
 
 D-Form
 
@@ -19,8 +19,9 @@ Pseudo-code:
 Description:
 
     Let the effective address (EA) be the sum (RA)+ D.
+
     (RS)[56:63] are stored into the byte in storage addressed
-    by EA. 
+    by RA.
 
     EA is placed into register RA.
 
@@ -30,7 +31,7 @@ Special Registers Altered:
 
     None
 
-# Store Byte with Update Indexed
+# Store Byte with Post-Update Indexed
 
 X-Form
 
@@ -46,6 +47,7 @@ Pseudo-code:
 Description:
 
     Let the effective address (EA) be the sum (RA)+ (RB).
+
     (RS)[56:63] are stored into the byte in storage addressed
     by EA.
 
@@ -57,7 +59,7 @@ Special Registers Altered:
 
     None
 
-# Store Halfword with Update
+# Store Halfword with Post-Update
 
 D-Form
 
@@ -70,11 +72,18 @@ Pseudo-code:
     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+ D.
+
+    (RS)[48:63] are stored into the halfword in storage
+    addressed by EA.
+
 Special Registers Altered:
 
     None
 
-# Store Halfword with Update Indexed
+# Store Halfword with Post-Update Indexed
 
 X-Form
 
@@ -87,11 +96,22 @@ Pseudo-code:
     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    (RS)[56:63] are stored into the byte in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid
+
 Special Registers Altered:
 
     None
 
-# Store Word with Update
+# Store Word with Post-Update
 
 D-Form
 
@@ -104,11 +124,22 @@ Pseudo-code:
     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+
+    (RS)[32:63] are stored into the word in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
 
-# Store Word with Update Indexed
+# Store Word with Post-Update Indexed
 
 X-Form
 
@@ -121,11 +152,22 @@ Pseudo-code:
     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    (RS)[32:63] are stored into the word in storage addressed
+    by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
 
-# Store Doubleword with Update
+# Store Doubleword with Post-Update
 
 DS-Form
 
@@ -138,11 +180,22 @@ Pseudo-code:
     MEM(ea, 8) <- (RS)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum.
+
+    (RA)+ (DS||0b00). (RS) is stored into the doubleword in
+    storage addressed by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
 
-# Store Doubleword with Update Indexed
+# Store Doubleword with Post-Update Indexed
 
 X-Form
 
@@ -155,6 +208,17 @@ Pseudo-code:
     MEM(ea, 8) <- (RS)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+
+    (RS) is stored into the doubleword in storage
+    addressed by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None