bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / pifixedstoreshift.mdwn

diff --git a/openpower/isa/pifixedstoreshift.mdwn b/openpower/isa/pifixedstoreshift.mdwn
index 93ea5dac9b4051c17a4b4fa4c7967678b90fac5a..43239d0c4832ccf76ac97555a0afefcc68dac3da 100644 (file)
--- a/openpower/isa/pifixedstoreshift.mdwn
+++ b/openpower/isa/pifixedstoreshift.mdwn
@@ -3,22 +3,26 @@
 <!-- This defines instructions that store from a register to RAM -->
 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
 
+<!-- https://bugs.libre-soc.org/show_bug.cgi?id=1055 -->
+<!-- https://libre-soc.org/openpower/sv/rfc/ls004/ -->
+
 # Store Byte with Post-Update Indexed
 
-X-Form
+Z23-Form
 
-* stbupx RS,RA,RB
+* stbupsx RS,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB)<<(SH+1)
     ea <- (RA)
     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
     RA <- EA
 
 Description:
 
-    Let the effective address (EA) be the sum (RA)+ (RB).
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and the contents of register RA.
 
     (RS)[56:63] are stored into the byte in storage addressed by EA.
 
@@ -32,20 +36,21 @@ Special Registers Altered:
 
 # Store Halfword with Post-Update Indexed
 
-X-Form
+Z23-Form
 
-* sthupx RS,RA,RB
+* sthupsx RS,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB)<<(SH+1)
     ea <- (RA)
     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
 
 Description:
 
-    Let the effective address (EA) be the sum (RA)+ (RB).
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and the contents of register RA.
 
     (RS)[56:63] are stored into the byte in storage addressed by EA.
 
@@ -59,20 +64,21 @@ Special Registers Altered:
 
 # Store Word with Post-Update Indexed
 
-X-Form
+Z23-Form
 
-* stwupx RS,RA,RB
+* stwupsx RS,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB)<<(SH+1)
     ea <- (RA)
     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
 
 Description:
 
-    Let the effective address (EA) be the sum (RA)+ (RB).
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and the contents of register RA.
 
     (RS)[32:63] are stored into the word in storage addressed by RA.
 
@@ -86,20 +92,21 @@ Special Registers Altered:
 
 # Store Doubleword with Post-Update Indexed
 
-X-Form
+Z23-Form
 
-* stdupx RS,RA,RB
+* stdupsx RS,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB)<<(SH+1)
     ea <- (RA)
     MEM(ea, 8) <- (RS)
     RA <- EA
 
 Description:
 
-    Let the effective address (EA) be the sum (RA)+ (RB).
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and the contents of register RA.
 
     (RS) is stored into the doubleword in storage addressed by RA.